📄 seq_gen.fit.rpt
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+----------------------------+------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 3.06) ; Number of LABs (Total = 4) ;
+----------------------------------------------+-----------------------------+
; 0 - 1 ; 12 ;
; 2 - 3 ; 1 ;
; 4 - 5 ; 0 ;
; 6 - 7 ; 0 ;
; 8 - 9 ; 0 ;
; 10 - 11 ; 0 ;
; 12 - 13 ; 2 ;
; 14 - 15 ; 0 ;
; 16 - 17 ; 0 ;
; 18 - 19 ; 0 ;
; 20 - 21 ; 0 ;
; 22 - 23 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 2.31) ; Number of LABs (Total = 4) ;
+----------------------------------------+-----------------------------+
; 0 ; 12 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 2 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 5 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.88) ; Number of LABs (Total = 3) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 13 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC8 ; clk_seq ; pix_clk ;
; A ; LC1 ; clk_seq, \diff:inputrega ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5] ;
; B ; LC20 ; clk_seq, \diff:inputregb, \diff:inputrega, \vcount:lcd_vz~18 ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5], lcd_vs~109, sync_out~386, lcd_dataen~298, blank_out~220, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0]~247sexp ;
; B ; LC17 ; clk_seq, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0], \diff:inputregb, \diff:inputrega, \vcount:lcd_vz~18 ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5], lcd_vs~109, sync_out~380, sync_out~386, lcd_dataen~298, blank_out~220, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0]~247sexp ;
; B ; LC32 ; clk_seq, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0], \diff:inputregb, \diff:inputrega, \vcount:lcd_vz~18 ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5], lcd_vs~109, lcd_dataen~298, blank_out~220, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0]~247sexp, sync_out~377bal ;
; B ; LC23 ; clk_seq, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0], \diff:inputregb, \diff:inputrega, \vcount:lcd_vz~18 ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9], lcd_vs~109, lcd_dataen~298, blank_out~220, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0]~247sexp, sync_out~377bal ;
; B ; LC29 ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1] ; lcd_vs_out ;
; B ; LC27 ; lcd_dataen~300, lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[8], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[7], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[6], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[4], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0] ; lcd_dataen ;
; B ; LC18 ; clk_seq, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0], \diff:inputregb, \diff:inputrega, \vcount:lcd_vz~18 ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5], lcd_vs~109, sync_out~386, lcd_dataen~298, blank_out~220, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0]~247sexp ;
; B ; LC25 ; blank_out~220, lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[3], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[2], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[8], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[4], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[1], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[6], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[7], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[5] ; blank_out ;
; B ; LC22 ; clk_seq, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0], \diff:inputregb, \diff:inputrega, \vcount:lcd_vz~18 ; lcd_vs~109, lcd_dataen~298, blank_out~220, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0]~247sexp, sync_out~377bal ;
; B ; LC24 ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[7], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[8], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[6], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[5] ; blank_out~218 ;
; B ; LC28 ; clk_seq, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0], \diff:inputregb, \diff:inputrega, \vcount:lcd_vz~18 ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9], lcd_vs~109, lcd_dataen~298, blank_out~220, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0]~247sexp, sync_out~377bal ;
; B ; LC30 ; clk_seq, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0], \diff:inputregb, \diff:inputrega, \vcount:lcd_vz~18 ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9], lcd_vs~109, lcd_dataen~298, blank_out~220, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0]~247sexp, sync_out~377bal ;
; B ; LC26 ; lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[5], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[8], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[7], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[6], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[4], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[3], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[2], lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[1] ; lcd_dataen~298 ;
; B ; LC31 ; clk_seq, lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1], lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0], \diff:inputregb, \diff:inputrega, \vcount:lcd_vz~18 ⌨️ 快捷键说明
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