📄 seq_gen.tan.qmsg

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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_seq register lpm_counter:\\hcount:hcountreg\[0\]_rtl_0\|dffs\[9\] register \\diff:inputrega 93.46 MHz 10.7 ns Internal " "Info: Clock \"clk_seq\" has Internal fmax of 93.46 MHz between source register \"lpm_counter:\\hcount:hcountreg\[0\]_rtl_0\|dffs\[9\]\" and destination register \"\\diff:inputrega\" (period= 10.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.200 ns + Longest register register " "Info: + Longest register to register delay is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:\\hcount:hcountreg\[0\]_rtl_0\|dffs\[9\] 1 REG LC75 41 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC75; Fanout = 41; REG Node = 'lpm_counter:\\hcount:hcountreg\[0\]_rtl_0\|dffs\[9\]'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "" { lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.800 ns) 6.200 ns \\diff:inputrega 2 REG LC177 11 " "Info: 2: + IC(3.400 ns) + CELL(2.800 ns) = 6.200 ns; Loc. = LC177; Fanout = 11; REG Node = '\\diff:inputrega'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "6.200 ns" { lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] \diff:inputrega } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 45.16 % " "Info: Total cell delay = 2.800 ns ( 45.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns 54.84 % " "Info: Total interconnect delay = 3.400 ns ( 54.84 % )" {  } {  } 0}  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "6.200 ns" { lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] \diff:inputrega } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.200 ns" { lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] \diff:inputrega } { 0.000ns 3.400ns } { 0.000ns 2.800ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_seq destination 3.200 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_seq\" to destination register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clk_seq 1 CLK PIN_87 23 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clk_seq'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "" { clk_seq } "NODE_NAME" } "" } } { "seq_gen.vhd" "" { Text "D:/work/fpga temple/seq_gen 576/seq_gen.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns \\diff:inputrega 2 REG LC177 11 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC177; Fanout = 11; REG Node = '\\diff:inputrega'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "0.800 ns" { clk_seq \diff:inputrega } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 100.00 % " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "3.200 ns" { clk_seq \diff:inputrega } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { clk_seq clk_seq~out \diff:inputrega } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_seq source 3.200 ns - Longest register " "Info: - Longest clock path from clock \"clk_seq\" to source register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clk_seq 1 CLK PIN_87 23 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clk_seq'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "" { clk_seq } "NODE_NAME" } "" } } { "seq_gen.vhd" "" { Text "D:/work/fpga temple/seq_gen 576/seq_gen.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns lpm_counter:\\hcount:hcountreg\[0\]_rtl_0\|dffs\[9\] 2 REG LC75 41 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC75; Fanout = 41; REG Node = 'lpm_counter:\\hcount:hcountreg\[0\]_rtl_0\|dffs\[9\]'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "0.800 ns" { clk_seq lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 100.00 % " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "3.200 ns" { clk_seq lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { clk_seq clk_seq~out lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0}  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "3.200 ns" { clk_seq \diff:inputrega } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { clk_seq clk_seq~out \diff:inputrega } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } } { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "3.200 ns" { clk_seq lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { clk_seq clk_seq~out lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } {  } 0}  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "6.200 ns" { lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] \diff:inputrega } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.200 ns" { lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] \diff:inputrega } { 0.000ns 3.400ns } { 0.000ns 2.800ns } } } { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "3.200 ns" { clk_seq \diff:inputrega } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { clk_seq clk_seq~out \diff:inputrega } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } } { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "3.200 ns" { clk_seq lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { clk_seq clk_seq~out lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_seq rgb lpm_counter:\\hcount:hcountreg\[0\]_rtl_0\|dffs\[9\] 21.600 ns register " "Info: tco from clock \"clk_seq\" to destination pin \"rgb\" through register \"lpm_counter:\\hcount:hcountreg\[0\]_rtl_0\|dffs\[9\]\" is 21.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_seq source 3.200 ns + Longest register " "Info: + Longest clock path from clock \"clk_seq\" to source register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clk_seq 1 CLK PIN_87 23 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clk_seq'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "" { clk_seq } "NODE_NAME" } "" } } { "seq_gen.vhd" "" { Text "D:/work/fpga temple/seq_gen 576/seq_gen.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns lpm_counter:\\hcount:hcountreg\[0\]_rtl_0\|dffs\[9\] 2 REG LC75 41 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC75; Fanout = 41; REG Node = 'lpm_counter:\\hcount:hcountreg\[0\]_rtl_0\|dffs\[9\]'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "0.800 ns" { clk_seq lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 100.00 % " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "3.200 ns" { clk_seq lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { clk_seq clk_seq~out lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.800 ns + Longest register pin " "Info: + Longest register to pin delay is 16.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:\\hcount:hcountreg\[0\]_rtl_0\|dffs\[9\] 1 REG LC75 41 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC75; Fanout = 41; REG Node = 'lpm_counter:\\hcount:hcountreg\[0\]_rtl_0\|dffs\[9\]'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "" { lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(1.300 ns) 4.700 ns rgb~1920 2 COMB LC65 1 " "Info: 2: + IC(3.400 ns) + CELL(1.300 ns) = 4.700 ns; Loc. = LC65; Fanout = 1; COMB Node = 'rgb~1920'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "4.700 ns" { lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] rgb~1920 } "NODE_NAME" } "" } } { "seq_gen.vhd" "" { Text "D:/work/fpga temple/seq_gen 576/seq_gen.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.300 ns) 8.000 ns rgb~1910 3 COMB LC66 1 " "Info: 3: + IC(0.000 ns) + CELL(3.300 ns) = 8.000 ns; Loc. = LC66; Fanout = 1; COMB Node = 'rgb~1910'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "3.300 ns" { rgb~1920 rgb~1910 } "NODE_NAME" } "" } } { "seq_gen.vhd" "" { Text "D:/work/fpga temple/seq_gen 576/seq_gen.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 15.200 ns rgb~1917 4 COMB LC72 1 " "Info: 4: + IC(3.200 ns) + CELL(4.000 ns) = 15.200 ns; Loc. = LC72; Fanout = 1; COMB Node = 'rgb~1917'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "7.200 ns" { rgb~1910 rgb~1917 } "NODE_NAME" } "" } } { "seq_gen.vhd" "" { Text "D:/work/fpga temple/seq_gen 576/seq_gen.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 16.800 ns rgb 5 PIN PIN_97 0 " "Info: 5: + IC(0.000 ns) + CELL(1.600 ns) = 16.800 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 'rgb'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "1.600 ns" { rgb~1917 rgb } "NODE_NAME" } "" } } { "seq_gen.vhd" "" { Text "D:/work/fpga temple/seq_gen 576/seq_gen.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.200 ns 60.71 % " "Info: Total cell delay = 10.200 ns ( 60.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.600 ns 39.29 % " "Info: Total interconnect delay = 6.600 ns ( 39.29 % )" {  } {  } 0}  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "16.800 ns" { lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] rgb~1920 rgb~1910 rgb~1917 rgb } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.800 ns" { lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] rgb~1920 rgb~1910 rgb~1917 rgb } { 0.000ns 3.400ns 0.000ns 3.200ns 0.000ns } { 0.000ns 1.300ns 3.300ns 4.000ns 1.600ns } } }  } 0}  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "3.200 ns" { clk_seq lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { clk_seq clk_seq~out lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } } { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "16.800 ns" { lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] rgb~1920 rgb~1910 rgb~1917 rgb } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.800 ns" { lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9] rgb~1920 rgb~1910 rgb~1917 rgb } { 0.000ns 3.400ns 0.000ns 3.200ns 0.000ns } { 0.000ns 1.300ns 3.300ns 4.000ns 1.600ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk_seq pix_clk 10.000 ns Longest " "Info: Longest tpd from source pin \"clk_seq\" to destination pin \"pix_clk\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clk_seq 1 CLK PIN_87 23 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clk_seq'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "" { clk_seq } "NODE_NAME" } "" } } { "seq_gen.vhd" "" { Text "D:/work/fpga temple/seq_gen 576/seq_gen.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(4.000 ns) 8.400 ns clk_seq~6 2 COMB LC8 1 " "Info: 2: + IC(2.000 ns) + CELL(4.000 ns) = 8.400 ns; Loc. = LC8; Fanout = 1; COMB Node = 'clk_seq~6'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "6.000 ns" { clk_seq clk_seq~6 } "NODE_NAME" } "" } } { "seq_gen.vhd" "" { Text "D:/work/fpga temple/seq_gen 576/seq_gen.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 10.000 ns pix_clk 3 PIN PIN_2 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 10.000 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'pix_clk'" {  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "1.600 ns" { clk_seq~6 pix_clk } "NODE_NAME" } "" } } { "seq_gen.vhd" "" { Text "D:/work/fpga temple/seq_gen 576/seq_gen.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" "" { Report "D:/work/fpga temple/seq_gen 576/db/seq_gen_cmp.qrpt" Compiler "seq_gen" "UNKNOWN" "V1" "D:/work/fpga temple/seq_gen 576/db/seq_gen.quartus_db" { Floorplan "D:/work/fpga temple/seq_gen 576/" "" "10.000 ns" { clk_seq clk_seq~6 pix_clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clk_seq clk_seq~out clk_seq~6 pix_clk } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.400ns 4.000ns 1.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 20 13:17:19 2005 " "Info: Processing ended: Tue Dec 20 13:17:19 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
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