seq_gen.map.qmsg

高清电视HDTV信号发生器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 20 13:16:55 2005 " "Info: Processing started: Tue Dec 20 13:16:55 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off seq_gen -c seq_gen " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seq_gen -c seq_gen" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seq_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seq_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seq_gen-rtl_seq_gen " "Info: Found design unit 1: seq_gen-rtl_seq_gen" {  } { { "seq_gen.vhd" "" { Text "D:/work/fpga temple/seq_gen 576/seq_gen.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 seq_gen " "Info: Found entity 1: seq_gen" {  } { { "seq_gen.vhd" "" { Text "D:/work/fpga temple/seq_gen 576/seq_gen.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "seq_gen " "Info: Elaborating entity \"seq_gen\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "\\hcount:hcountreg\[0\]~0 10 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: \"\\hcount:hcountreg\[0\]~0\"" {  } {  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "\\vcount:vcountreg\[0\]~0 10 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: \"\\vcount:vcountreg\[0\]~0\"" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk_seq " "Info: Promoted clock signal driven by pin \"clk_seq\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "59 " "Info: Implemented 59 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "37 " "Info: Implemented 37 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "14 " "Info: Implemented 14 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 20 13:17:05 2005 " "Info: Processing ended: Tue Dec 20 13:17:05 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0}  } {  } 0}