seq_gen.vhd

高清电视HDTV信号发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity seq_gen is
	port(clk_seq : in std_logic;
		rst_seq : in std_logic;
		sync_out : out std_logic;
		blank_out : out std_logic;
		rgb : out std_logic;
		lcd_dataen : out std_logic;
		lcd_vs_out : out std_logic;
		pix_clk : out std_logic );
end seq_gen;

architecture rtl_seq_gen of seq_gen is
	signal lcd_hb : std_logic;
	signal sync : std_logic;
	signal v_sync : std_logic;
	signal c_sync : std_logic;
	signal lcd_vb : std_logic;
	signal lcd_vs : std_logic;
	signal blank : std_logic;	
	signal vs : std_logic;	
	signal clken_vcount : std_logic;

begin

	hcount: block

	signal hcountreg :std_logic_vector(9 downto 0);
	signal hz_temp : std_logic;
	signal lcd_hz : std_logic;

	begin

	process (clk_seq,lcd_hz)

		begin

		if (lcd_hz = '1') then
		hcountreg <= (others =>'0');
		elsif clk_seq'event and clk_seq = '1' then
		hcountreg <= hcountreg +1;
		end if;

	end process;

	lcd_hb <= '0' when hcountreg >=600 and hcountreg < 650
	else '1';
	sync <='0' when hcountreg >=0 and hcountreg < 64
	else '1';
	rgb <='1' when (hcountreg >=187 and hcountreg < 189)
				or (hcountreg >=232 and hcountreg < 234)
				or (hcountreg >=277 and hcountreg < 279)
				or (hcountreg >=322 and hcountreg < 324)
				or (hcountreg >=367 and hcountreg < 369)
				or (hcountreg >=412 and hcountreg < 414)
				or (hcountreg >=457 and hcountreg < 459)
				or (hcountreg >=502 and hcountreg < 504)
				or (hcountreg >=547 and hcountreg < 549)
				or (hcountreg >=592 and hcountreg < 594)
				or (hcountreg >=637 and hcountreg < 639)
				or (hcountreg >=682 and hcountreg < 684)
				or (hcountreg >=727 and hcountreg < 729)
				or (hcountreg >=772 and hcountreg < 774)
				or (hcountreg >=817 and hcountreg < 819)
	else '0';
	blank <='1' when hcountreg >=142 and hcountreg < 862
	else '0';
	v_sync <='0' when hcountreg >=0 and hcountreg < 849
	else '1';
	hz_temp <= '1' when hcountreg = 864 else '0';--一个行周期
	lcd_hz <=hz_temp or rst_seq;

end block hcount;

diff : block

signal inputrega : std_logic;
signal inputregb : std_logic;

begin

	process(clk_seq)

	begin

		if clk_seq'event and clk_seq='1' then
		inputregb <= inputrega;
		inputrega <= not sync;
		end if;

	end process;

clken_vcount <= not inputregb and inputrega;

end block diff;

vcount : block

signal vcountreg : std_logic_vector(9 downto 0);
signal vz_temp : std_logic;
signal lcd_vz : std_logic;

begin

	process (clk_seq,lcd_vz)

	begin

	if(lcd_vz='1')then
	vcountreg <= (others => '0');
	elsif clk_seq'event and clk_seq = '1' then
	if clken_vcount = '1' then
	vcountreg <= vcountreg +1;
	end if;
	end if;

	end process;

lcd_vb <= '0' when vcountreg >=600 and vcountreg < 615
else '1';
lcd_vs <='0' when vcountreg >= 5 and vcountreg < 10
else '1';
vs <='0' when vcountreg >= 0 and vcountreg < 49
else '1';
vz_temp <= '1' when vcountreg = 625 else '0';
lcd_vz <= vz_temp or rst_seq;

end block vcount;

pix_clk <=clk_seq;
lcd_dataen <=lcd_hb and lcd_vb;
c_sync <= (not lcd_vs) and v_sync;
sync_out <=(sync and lcd_vs) or c_sync;
lcd_vs_out <=lcd_vs;
blank_out <= vs and blank;

end rtl_seq_gen;