seq_gen.tan.rpt

高清电视HDTV信号发生器

; N/A   ; None         ; 13.700 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3] ; lcd_dataen ; clk_seq    ;
; N/A   ; None         ; 13.700 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2] ; lcd_dataen ; clk_seq    ;
; N/A   ; None         ; 13.700 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1] ; lcd_dataen ; clk_seq    ;
; N/A   ; None         ; 13.700 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0] ; lcd_dataen ; clk_seq    ;
; N/A   ; None         ; 13.700 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2] ; sync_out   ; clk_seq    ;
; N/A   ; None         ; 13.700 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0] ; sync_out   ; clk_seq    ;
; N/A   ; None         ; 13.700 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[3] ; lcd_vs_out ; clk_seq    ;
; N/A   ; None         ; 13.700 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[2] ; lcd_vs_out ; clk_seq    ;
; N/A   ; None         ; 13.700 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[1] ; lcd_vs_out ; clk_seq    ;
; N/A   ; None         ; 13.700 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[0] ; lcd_vs_out ; clk_seq    ;
; N/A   ; None         ; 13.700 ns  ; lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[1] ; blank_out  ; clk_seq    ;
; N/A   ; None         ; 13.700 ns  ; lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[2] ; blank_out  ; clk_seq    ;
; N/A   ; None         ; 13.700 ns  ; lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[3] ; blank_out  ; clk_seq    ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6] ; lcd_dataen ; clk_seq    ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5] ; lcd_dataen ; clk_seq    ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4] ; lcd_dataen ; clk_seq    ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9] ; lcd_dataen ; clk_seq    ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8] ; lcd_dataen ; clk_seq    ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7] ; lcd_dataen ; clk_seq    ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[6] ; lcd_vs_out ; clk_seq    ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[5] ; lcd_vs_out ; clk_seq    ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[4] ; lcd_vs_out ; clk_seq    ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[9] ; lcd_vs_out ; clk_seq    ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[8] ; lcd_vs_out ; clk_seq    ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:\vcount:vcountreg[0]_rtl_1|dffs[7] ; lcd_vs_out ; clk_seq    ;
+-------+--------------+------------+------------------------------------------------+------------+------------+


+-----------------------------------------------------------------+
; tpd                                                             ;
+-------+-------------------+-----------------+---------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From    ; To      ;
+-------+-------------------+-----------------+---------+---------+
; N/A   ; None              ; 10.000 ns       ; clk_seq ; pix_clk ;
+-------+-------------------+-----------------+---------+---------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Tue Dec 20 13:17:17 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seq_gen -c seq_gen
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_seq" is an undefined clock
Info: Clock "clk_seq" has Internal fmax of 93.46 MHz between source register "lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9]" and destination register "\diff:inputrega" (period= 10.7 ns)
    Info: + Longest register to register delay is 6.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC75; Fanout = 41; REG Node = 'lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9]'
        Info: 2: + IC(3.400 ns) + CELL(2.800 ns) = 6.200 ns; Loc. = LC177; Fanout = 11; REG Node = '\diff:inputrega'
        Info: Total cell delay = 2.800 ns ( 45.16 % )
        Info: Total interconnect delay = 3.400 ns ( 54.84 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk_seq" to destination register is 3.200 ns
            Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clk_seq'
            Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC177; Fanout = 11; REG Node = '\diff:inputrega'
            Info: Total cell delay = 3.200 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk_seq" to source register is 3.200 ns
            Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clk_seq'
            Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC75; Fanout = 41; REG Node = 'lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9]'
            Info: Total cell delay = 3.200 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: tco from clock "clk_seq" to destination pin "rgb" through register "lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9]" is 21.600 ns
    Info: + Longest clock path from clock "clk_seq" to source register is 3.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clk_seq'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC75; Fanout = 41; REG Node = 'lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9]'
        Info: Total cell delay = 3.200 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 16.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC75; Fanout = 41; REG Node = 'lpm_counter:\hcount:hcountreg[0]_rtl_0|dffs[9]'
        Info: 2: + IC(3.400 ns) + CELL(1.300 ns) = 4.700 ns; Loc. = LC65; Fanout = 1; COMB Node = 'rgb~1920'
        Info: 3: + IC(0.000 ns) + CELL(3.300 ns) = 8.000 ns; Loc. = LC66; Fanout = 1; COMB Node = 'rgb~1910'
        Info: 4: + IC(3.200 ns) + CELL(4.000 ns) = 15.200 ns; Loc. = LC72; Fanout = 1; COMB Node = 'rgb~1917'
        Info: 5: + IC(0.000 ns) + CELL(1.600 ns) = 16.800 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 'rgb'
        Info: Total cell delay = 10.200 ns ( 60.71 % )
        Info: Total interconnect delay = 6.600 ns ( 39.29 % )
Info: Longest tpd from source pin "clk_seq" to destination pin "pix_clk" is 10.000 ns
    Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_87; Fanout = 23; CLK Node = 'clk_seq'
    Info: 2: + IC(2.000 ns) + CELL(4.000 ns) = 8.400 ns; Loc. = LC8; Fanout = 1; COMB Node = 'clk_seq~6'
    Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 10.000 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'pix_clk'
    Info: Total cell delay = 8.000 ns ( 80.00 % )
    Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Dec 20 13:17:19 2005
    Info: Elapsed time: 00:00:02