ym3_8.txt

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library ieee;
use ieee.std_logic_1164.all;

entity ym3_8 is
	port(a0,a1,a2:in bit;
			s1,s2,s3:in bit;
			y0,y1,y2,y3,y4,y5,y6,y7:out bit);
end ym3_8;

architecture rtl of ym3_8 is
	signal s:bit;
	signal a:bit_vector(2 downto 0);
	signal y:bit_vector(7 downto 0);
begin
	process(a,s1,s2,s3)
	begin
		s<=s2 or s3;
		a<=a2&a1&a0;
			if s1='0' then
				y<="11111111";
			elsif s='1' then
				y<="11111111";
			else
			case a is
		when"000"=>y<="11111110";
		when"001"=>y<="11111101";
		when"010"=>y<="11111011";
		when"011"=>y<="11110111";
		when"100"=>y<="11101111";
		when"101"=>y<="11011111";
		when"110"=>y<="10111111";
		when"111"=>y<="01111111";
	end case;
	end if;
end process;
y0<=y(0);
y1<=y(1);
y2<=y(2);
y3<=y(3);
y4<=y(4);
y5<=y(5);
y6<=y(6);
y7<=y(7);


end rtl;