serial_interface.v

一个在FPGA芯片上实现UART功能的vhdl源代码

//
// Module UART_V.serial_interface.struct
//
// Created:
//          by - user.group (host.domain)
//          at - 10:56:06 30 Aug 2001
//
// Generated by Mentor Graphics' HDL Designer(TM) 2001.5
//

`resetall
`timescale 1ns/10ps
module serial_interface( 
   clear_flags, 
   clk, 
   data_in, 
   enable_write, 
   rst, 
   sample, 
   ser_if_select, 
   sin, 
   start_xmit, 
   xmitdt_en, 
   enable_rcv_clk, 
   enable_xmit_clk, 
   int, 
   ser_if_data, 
   sout
);


// Internal Declarations

input        clear_flags;
input        clk;
input  [7:0] data_in;
input        enable_write;
input        rst;
input        sample;
input  [1:0] ser_if_select;
input        sin;
input        start_xmit;
input        xmitdt_en;
output       enable_rcv_clk;
output       enable_xmit_clk;
output       int;
output [7:0] ser_if_data;
output       sout;


wire        clear_flags;
wire        clk;
wire [7:0]  data_in;
wire        enable_write;
wire        rst;
wire        sample;
wire [1:0]  ser_if_select;
wire        sin;
wire        start_xmit;
wire        xmitdt_en;
wire        enable_rcv_clk;
wire        enable_xmit_clk;
wire        int;
wire [7:0]  ser_if_data;
wire        sout;

// Local declarations


   
// Internal signal declarations
wire       done_rcving;
wire       done_xmitting;
wire [2:0] rcv_bit_cnt;
wire       rcving;
wire       read_bit;
wire [7:0] recvdt;
wire [7:0] status;
wire [7:0] xmitdt;
wire       xmitting;
wire [7:0] zeros;


// ModuleWare signal declarations for instance 'ser_out_mux' of 'mux4'
wire [7:0] MW_ser_out_muxdin0l;
wire [7:0] MW_ser_out_muxdin1l;
wire [7:0] MW_ser_out_muxdin2l;
wire [7:0] MW_ser_out_muxdin3l;
reg [7:0] MW_ser_out_muxdtempl;

reg [7:0] xmitdt_reg, recvdt_reg;

// Instances 
status_registers I1( 
   .clear_flags   (clear_flags), 
   .clk           (clk), 
   .done_rcving   (done_rcving), 
   .done_xmitting (done_xmitting), 
   .rcving        (rcving), 
   .rst           (rst), 
   .xmitting      (xmitting), 
   .int           (int), 
   .status        (status)
); 

xmit_rcv_control I0( 
   .clk             (clk), 
   .rst             (rst), 
   .sample          (sample), 
   .sin             (sin), 
   .start_xmit      (start_xmit), 
   .xmitdt          (xmitdt), 
   .done_rcving     (done_rcving), 
   .done_xmitting   (done_xmitting), 
   .enable_rcv_clk  (enable_rcv_clk), 
   .enable_xmit_clk (enable_xmit_clk), 
   .rcv_bit_cnt     (rcv_bit_cnt), 
   .rcving          (rcving), 
   .read_bit        (read_bit), 
   .sout            (sout), 
   .xmitting        (xmitting)
); 

// ModuleWare instances.

// HDL Embedded Block 1 convert
// Non hierarchical flowchart

///////////////////////////////////////////////////////////////////////////
// Flowchart conv
always @ (posedge clk or negedge rst)
begin : conv
   // Asynchronous Reset
   if (!rst) begin
      // Reset Actions
      xmitdt_reg = 0;
      recvdt_reg = 0;

   end
   else begin
      if (xmitdt_en  && enable_write) begin
         xmitdt_reg = data_in;
      end
      else if (read_bit) begin
         recvdt_reg[rcv_bit_cnt] = sin;
      end

   end
end

// Concurrent statements
assign xmitdt = xmitdt_reg;
assign recvdt = recvdt_reg;


// ModuleWare code for instance 'zeros' of 'constvec'

   assign zeros = 8'd0;

// ModuleWare code for instance 'ser_out_mux' of 'mux4'
always @(MW_ser_out_muxdin0l or MW_ser_out_muxdin1l or MW_ser_out_muxdin2l or MW_ser_out_muxdin3l or ser_if_select) begin
case (ser_if_select)
   2'd0: MW_ser_out_muxdtempl = MW_ser_out_muxdin0l;
   2'd1: MW_ser_out_muxdtempl = MW_ser_out_muxdin1l;
   2'd2: MW_ser_out_muxdtempl = MW_ser_out_muxdin2l;
   default: MW_ser_out_muxdtempl = MW_ser_out_muxdin3l;
endcase
end
assign ser_if_data = MW_ser_out_muxdtempl;
assign MW_ser_out_muxdin0l = xmitdt;
assign MW_ser_out_muxdin1l = recvdt;
assign MW_ser_out_muxdin2l = status;
assign MW_ser_out_muxdin3l = zeros;
endmodule // serial_interface