myuartcore.vhd

串口通讯源码

----------------------------------------------------------------------------------
-- Company: Xidian University Computer
-- Engineer: jefby
-- 
-- Create Date:    20:20:34 11/06/2012 
-- Design Name:    MyUart
-- Module Name:    MyUartCore - Behavioral 
-- Project Name:  MyUart
-- Target Devices: Spartan-3E
-- Tool versions: 
-- Description: 在SPARTAN-3E上利用SW来输入值，并通过串口传递给PC，或者从PC端接收数据，并在LED灯上显示其ACSII值。
-- 工具使用说明详见readme.pdf
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MyUartCore is
	generic (DATA_WIDTH : integer := 8);
	port(
	--input 
	--data,clk,rst 
			rxd : in	  std_logic;
			di : in std_logic_vector(DATA_WIDTH - 1 downto 0);
			sys_clk_50MHZ,rst_p  : in std_logic;
			en:in std_logic;
	--output 
	--rxd,data
		   txd : out  std_logic;
			do : out std_logic_vector(DATA_WIDTH - 1 downto 0)
	);
end MyUartCore;

architecture Behavioral of MyUartCore is

--波特率生成器
component baud_gen 
	generic(BAUD_VALUE : integer := 9600);
	port(
			sys_clk_50MHZ : in std_logic;
			rst_p	: in std_logic;
			bclk : out std_logic
	);
end component;

--接收模块
component recv 
	generic (DATA_WIDTH : integer := 8);
	port(
			rxd : in std_logic; --rxd data line 
			RDA : inout std_logic;--Read Data Avaliable Bit
			bclk : in std_logic;--bclk signal
			rst_p : in std_logic;--rst_p signal 
			dbout : out std_logic_vector(DATA_WIDTH-1 downto 0)--rxd_data
	);
end component;

--发送模块
component transfer 
	port(
		sys_clk_50MHZ : in std_logic;
		txd : out std_logic;
		dbin : in std_logic_vector(7 downto 0);
		bclk : in std_logic;
		rst_p : in std_logic;
		TBE	: inout std_logic 	:= '1';			--Transfer Bus Empty
		WR		: in  std_logic					--Write Strobe
	);
end component;

	signal bclk : std_logic := '0';
	signal tbe: std_logic;
	signal RDA : std_logic;
begin

	uut_baud_gen : baud_gen port map(sys_clk_50MHZ,rst_p,bclk);
	uut_transfer : transfer port map(sys_clk_50MHZ,txd,di,bclk,rst_p,tbe,en);
	uut_recv : recv port map(rxd,RDA,bclk,rst_p,do);

end Behavioral;