baud_gen_test.vhd

串口通讯源码

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-- Company: 
-- Engineer:
--
-- Create Date:   20:40:27 11/06/2012
-- Design Name:   
-- Module Name:   D:/Project/Xilinx Project/My_Own/MyUart/baud_gen_test.vhd
-- Project Name:  MyUart
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: baud_gen
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY baud_gen_test IS
END baud_gen_test;
 
ARCHITECTURE behavior OF baud_gen_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT baud_gen
	 generic(BAUD_VALUE : integer := 9600);
    PORT(
         sys_clk_50MHZ : IN  std_logic;
         rst_p : IN  std_logic;
         bclk : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal sys_clk_50MHZ : std_logic := '0';
   signal rst_p : std_logic := '0';

 	--Outputs
   signal bclk : std_logic;

   -- Clock period definitions
   constant sys_clk_50MHZ_period : time := 20 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: baud_gen 
			generic map(BAUD_VALUE => 9600)
			PORT MAP (
          sys_clk_50MHZ => sys_clk_50MHZ,
          rst_p => rst_p,
          bclk => bclk
        );

   -- Clock process definitions
   sys_clk_50MHZ_process :process
   begin
		sys_clk_50MHZ <= '0';
		wait for sys_clk_50MHZ_period/2;
		sys_clk_50MHZ <= '1';
		wait for sys_clk_50MHZ_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
		rst_p <= '1';
      wait for 100 ns;	
		rst_p <= '0';
		
      wait for sys_clk_50MHZ_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;