recv.vhd

串口通讯源码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:21:15 11/06/2012 
-- Design Name: 
-- Module Name:    recv - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity recv is
	generic (DATA_WIDTH : integer := 8);
	port(
			rxd : in std_logic; --rxd data line 
			RDA : inout std_logic;--Read Data Avaliable Bit
			bclk : in std_logic;--bclk signal
			rst_p : in std_logic;--rst_p signal 
			dbout : out std_logic_vector(DATA_WIDTH-1 downto 0)--rxd_data
	);
end recv;

architecture Behavioral of recv is
	
	--Receive state machine
	type rstate is (					  
		strIdle,			--Idle state
		strEightDelay,	--Delays for 8 clock cycles
		strGetData,		--Shifts in the 8 data bits, and checks parity
		strCheckStop		--Sets framing error flag if Stop bit is wrong
	);
	
	--used for delay times
	signal ctr		:  std_logic_vector(3 downto 0)	:= "0000";
	--Counts the number of read data bits
	signal dataCtr :  std_logic_vector(3 downto 0)	:= "0000";	
	
	--Current state in the Receive state machine
	signal strCur	:  rstate	:= strIdle; 	
	--Next state in the Receive state machine
	signal strNext :  rstate 	;
	signal rShift : std_logic	;
	signal rdSReg : std_logic_vector(9 downto 0) := (others => '1');
	signal rdReg : std_logic_vector(7 downto 0);
	signal dataRST ,ctRst ,dataIncr: std_logic ;
	--signal RDA : std_logic;
	signal CE : std_logic;
	
begin

		dbout <= rdReg when RDA = '1' else
						(others => 'Z');

		---更改当前状态
		process (bclk, rst_p, CE)
		begin
			if rst_p = '1' then
				RDA <= '0';
			elsif bclk = '1' and bclk'event then
				if CE = '1' then
					RDA <= '1';	 
					rdReg(7 downto 0) <= rdSReg (7 downto 0);
				end if;				
			end if;
		end process;
		
		--set up a counter based on bclk
		process (bclk, ctRst)				   			
		begin
			if bclk = '1' and bclk'Event then
				if ctRst = '1' then
					ctr <= "0000";
				else
					ctr <= ctr + 1;
				end if;
			end if;
		end process;
		
		--This process controls the receiving shift register--
		process (bclk, rShift)
		begin
			if bclk = '1' and bclk'event then
				if rShift = '1' then
					rdSReg <= (RXD & rdSReg(9 downto 1));
				end if;
			end if;
		end process;
		
		--This process controls the dataCtr to keep track of shifted values--
		process (bclk, dataRST)
		begin
			if (bclk = '1' and bclk'event) then
				if dataRST = '1' then
					dataCtr <= "0000";
				elsif dataIncr = '1' then
					dataCtr <= dataCtr +1;
				end if;
			end if;
		end process;
		
		--Receiving State Machine--
		process (bclk, rst_p)
		begin
			if bclk = '1' and bclk'event then
				if rst_p = '1' then
					strCur <= strIdle;
				else
					strCur <= strNext;
				end if;
			end if;
		end process;
		
		--This process generates the sequence of steps needed receive the data
		process (strCur, ctr, rxd, dataCtr, rdSReg, rdReg, RDA)
		begin   
			case strCur is
				--当前状态为空闲状态，设置相应的控制位，并
				when strIdle =>
					dataIncr <= '0';
					rShift <= '0';
					dataRst <= '0';
					CE <= '0';
					
					--若检测到RXD信号为低，则进入等待8个时钟等待状态
					if RXD = '0' then
						ctRst <= '1';
						strNext <= strEightDelay;
					else
						ctRst <= '0';
						strNext <= strIdle;
					end if;
					
				--当前状态为8个时钟等待状态
				when strEightDelay => 
				
					dataIncr <= '0';
					rShift <= '0';
					CE <= '0';
					--8个周期到达，设置标志位，并设置下一状态为取数据阶段
					if ctr(2 downto 0) = "111" then
						ctRst <= '1';
					   dataRST <= '1';
						strNext <= strGetData;
					else
						ctRst <= '0';
						dataRST <= '0';
						strNext <= strEightDelay;
					end if;
				--取数据阶段
				when strGetData =>	
					CE <= '0';
					dataRst <= '0';
					--如果已经等待15个周期，设置数据加1标志位，同时移位标志位标为'1'
					if ctr(3 downto 0) = "1111" then
						ctRst <= '1';
						dataIncr <= '1';
						rShift <= '1';
					else
						ctRst <= '0';
						dataIncr <= '0';
						rShift <= '0';		
					end if;
					--如果已经取得了10位，进入检测停止位状态
					if dataCtr = "1010" then
						strNext <= strCheckStop;
					else
						strNext <= strGetData;
					end if;
				--检测停止位
				when strCheckStop =>
				
					dataIncr <= '0';
					rShift <= '0';
					dataRst <= '0';
					ctRst <= '0';
					CE <= '1';
					strNext <= strIdle;
									
			end case;
		
		end process;
		
end Behavioral;