top.twr

来自「串口通讯源码」· TWR 代码 · 共 71 行

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Release 14.2 Trace  (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4
-n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf top.ucf

Design file:              top.ncd
Physical constraint file: top.pcf
Device,package,speed:     xc3s500e,fg320,-4 (PRODUCTION 1.27 2012-07-09)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock sys_clk_50MHZ
------------+------------+------------+-------------------+--------+
            |Max Setup to|Max Hold to |                   | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s)  | Phase  |
------------+------------+------------+-------------------+--------+
en          |    4.638(R)|    1.046(R)|sys_clk_50MHZ_BUFGP|   0.000|
rst_p       |    2.998(R)|   -0.904(R)|sys_clk_50MHZ_BUFGP|   0.000|
------------+------------+------------+-------------------+--------+

Clock to Setup on destination clock sys_clk_50MHZ
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
sys_clk_50MHZ  |    7.154|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Mon Nov 12 21:21:25 2012 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 168 MB