baud_gen.vhd

来自「串口通讯源码」· VHDL 代码 · 共 82 行

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:30:10 11/06/2012 
-- Design Name: 
-- Module Name:    baud_gen - Behavioral 
-- Project Name:   MyUart
-- Target Devices: 
-- Tool versions: 
-- Description: 波特率发生器模块，可以进行灵活设置，BAUD_VALUE可以配置为9600bps，
--				    115200bps等参数，从而生成不同的波特时钟bclk
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity baud_gen is
	generic(BAUD_VALUE : integer := 9600);
	port(
			sys_clk_50MHZ : in std_logic;
			rst_p	: in std_logic;
			bclk : out std_logic
	);
end baud_gen;

architecture Behavioral of baud_gen is
	constant DIV_VALUE :integer := 50000000/BAUD_VALUE/16/2;
	signal count : std_logic_vector(31 downto 0) := (others => '0');
	signal bclk_pad : std_logic;

	
begin
   --生成计数器模块
	process(sys_clk_50MHZ,rst_p)
	begin
		if(rst_p = '1')then
			--bclk_pad <= '0';
			count <= (others => '0');
		elsif(rising_edge(sys_clk_50MHZ))then
			if(count = DIV_VALUE)then
				count <= (others => '0');
			else
				count <= count + '1';
			end if;
		end if;
	end process;
	--生成时钟
	process(sys_clk_50MHZ,rst_p)
	begin
		if(rst_p = '1')then
			bclk_pad <= '0';
		elsif(rising_edge(sys_clk_50MHZ))then
			if(count = DIV_VALUE)then
				bclk_pad <= not bclk_pad;
			end if;
		end if;
	end process;
	--
	bclk <= bclk_pad;
	


end Behavioral;