top.par

串口通讯源码

Release 14.2 par P.28xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

JEFBY-PC::  Mon Nov 12 21:20:57 2012

par -w -intstyle ise -ol high -t 1 top_map.ncd top.ncd top.pcf 


Constraints file: top.pcf.
Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx\14.2\ISE_DS\ISE\.
   "top" is an NCD, version 3.2, device xc3s500e, package fg320, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.27 2012-07-09".


Design Summary Report:

 Number of External IOBs                          17 out of 232     7%

   Number of External Input IOBs                  8

      Number of External Input IBUFs              8
        Number of LOCed External Input IBUFs      8 out of 8     100%


   Number of External Output IOBs                 9

      Number of External Output IOBs              9
        Number of LOCed External Output IOBs      9 out of 9     100%


   Number of External Bidir IOBs                  0


   Number of BUFGMUXs                        2 out of 24      8%
   Number of Slices                        102 out of 4656    2%
      Number of SLICEMs                      1 out of 2328    1%



Overall effort level (-ol):   High 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 


Starting Placer
Total REAL time at the beginning of Placer: 4 secs 
Total CPU  time at the beginning of Placer: 3 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:2cbcfdf4) REAL time: 5 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:2cbcfdf4) REAL time: 5 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:2cbcfdf4) REAL time: 5 secs 

Phase 4.2  Initial Clock and IO Placement

Phase 4.2  Initial Clock and IO Placement (Checksum:bbac0d8c) REAL time: 8 secs 

Phase 5.30  Global Clock Region Assignment
Phase 5.30  Global Clock Region Assignment (Checksum:bbac0d8c) REAL time: 8 secs 

Phase 6.36  Local Placement Optimization
Phase 6.36  Local Placement Optimization (Checksum:bbac0d8c) REAL time: 8 secs 

Phase 7.8  Global Placement
..............
....
...................
..
..
Phase 7.8  Global Placement (Checksum:635e7706) REAL time: 9 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:635e7706) REAL time: 9 secs 

Phase 9.18  Placement Optimization
Phase 9.18  Placement Optimization (Checksum:c42ccd58) REAL time: 9 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:c42ccd58) REAL time: 9 secs 

Total REAL time to Placer completion: 9 secs 
Total CPU  time to Placer completion: 7 secs 
Writing design to file top.ncd



Starting Router


Phase  1  : 653 unrouted;      REAL time: 15 secs 

Phase  2  : 579 unrouted;      REAL time: 15 secs 

Phase  3  : 105 unrouted;      REAL time: 15 secs 

Phase  4  : 115 unrouted; (Par is working to improve performance)     REAL time: 16 secs 

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 16 secs 

Updating file: top.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 16 secs 

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 19 secs 

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 19 secs 

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 19 secs 

Phase 10  : 0 unrouted; (Par is working to improve performance)     REAL time: 19 secs 
WARNING:Route:455 - CLK Net:uut_uart_core/uut_transfer/stbeCur_FSM_FFd1 may have excessive skew because 
      1 CLK pins and 5 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:uut_uart_core/uut_transfer/rClkDiv<3> may have excessive skew because 
      0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 19 secs 
Total CPU time to Router completion: 16 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|uut_uart_core/uut_ba |              |      |      |            |             |
|     ud_gen/bclk_pad | BUFGMUX_X1Y10| No   |   18 |  0.033     |  0.180      |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_50MHZ_BUFGP | BUFGMUX_X1Y11| No   |   31 |  0.051     |  0.190      |
+---------------------+--------------+------+------+------------+-------------+
|uut_uart_core/uut_tr |              |      |      |            |             |
|   ansfer/rClkDiv<3> |         Local|      |   13 |  0.103     |  1.982      |
+---------------------+--------------+------+------+------------+-------------+
|uut_uart_core/uut_tr |              |      |      |            |             |
|ansfer/stbeCur_FSM_F |              |      |      |            |             |
|                 Fd1 |         Local|      |    6 |  0.000     |  1.072      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net uut | SETUP       |         N/A|     4.570ns|     N/A|           0
  _uart_core/uut_baud_gen/bclk_pad          | HOLD        |     1.004ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net uut | SETUP       |         N/A|     3.412ns|     N/A|           0
  _uart_core/uut_transfer/rClkDiv<3>        | HOLD        |     1.011ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net sys | SETUP       |         N/A|     7.154ns|     N/A|           0
  _clk_50MHZ_BUFGP                          | HOLD        |     1.244ns|            |       0|           0
----------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 20 secs 
Total CPU time to PAR completion: 17 secs 

Peak Memory Usage:  314 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 2
Number of info messages: 1

Writing design to file top.ncd



PAR done!