📄 debounce_circut.vhd
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----------------------------------------------------------------------------------
-- Company: Xidian University Computer
-- Engineer: jefby
--
-- Create Date: 00:35:04 11/11/2012
-- Design Name: MyUart
-- Module Name: debounce_circut - Behavioral
-- Project Name: MyUart
-- Target Devices: Spartan-3E
-- Tool versions:
-- Description: 本程序是是实现了按键的消抖
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity debounce_circut is
port(
sys_clk,reset : std_logic;
sw : in std_logic;
db_level,db_tick : out std_logic
);
end debounce_circut;
architecture Behavioral of debounce_circut is
constant N : integer := 21;
type state_type is (zero,wait0,one,wait1);
signal state_reg,state_next : state_type;
signal q_reg,q_next: std_logic_vector(N-1 downto 0);
signal q_load,q_dec,q_zero : std_logic;
begin
process(sys_clk,reset)
begin
if(reset = '1')then
state_reg <= zero;
q_reg <= (others => '0');
elsif(rising_edge(sys_clk))then
state_reg <= state_next;
q_reg <= q_next;
end if;
end process;
q_next <= (others => '1') when q_load = '1' else
q_reg - 1 when q_dec = '1' else
q_reg;
q_zero <= '1' when q_next = 0 else '0';
process(state_reg,sw,q_zero)
begin
q_load <= '0';
q_dec <= '0';
db_tick <= '0';
state_next <= state_reg;
case state_reg is
when zero =>
db_level <= '0';
if(sw = '1')then
state_next <= wait1;
q_load <= '1';
end if;
when wait1 =>
db_level <= '0';
if(sw = '1')then
q_dec <= '1';
if(q_zero = '1')then
state_next <= one;
db_tick <= '1';--这儿是消抖后的信号
end if;
else--sw = '0'
state_next <= zero;
end if;
when one =>
db_level <= '1';
if(sw = '0')then
state_next <= wait0;
q_load <= '1';
end if;
when wait0 =>
db_level <= '1';
if(sw = '0')then
q_dec <= '1';
if(q_zero = '1')then
state_next <= zero;
end if;
else
state_next <= one;
end if;
end case;
end process;
end Behavioral;
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