top.vhd

串口通讯源码

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-- Company: Xidian University Computer
-- Engineer: jefby
-- 
-- Create Date:    20:39:20 11/10/2012 
-- Design Name:    MyUart
-- Module Name:    top - Behavioral 
-- Project Name:   MyUart
-- Target Devices: Spartan-3E
-- Tool versions: 
-- Description: 
-- 这段代码作用是按键消抖检测，
-- 当有按键按下，即btn_0 = '1'，计数器启动开始计数，并且不断检测按键的状态。如果是抖动，计数器会被清零；
 
-- 如果按键闭合状态时的电平保持一段时间不发生变化，我们就认为当前有按键按下。同理，按键释放时也会执行类似的过程。
-- 按上述分析，我们会得到如下结论：btn0_reg出现上升沿代表有按键按下。
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
	port(
		rxd : in std_logic;
		txd : out std_logic;
		sys_clk_50MHZ : in std_logic;
		rst_p : in std_logic;
		led : out std_logic_vector(7 downto 0);
		sw : in std_logic_vector(3 downto 0);
		en : in std_logic
	);

end top;

architecture Behavioral of top is


component keydwn_check 
     Port ( 
				btn_0 : in  STD_LOGIC;
            clk : in  STD_LOGIC;
            en : out  STD_LOGIC
			 );
end component;

component MyUartCore 
	generic (DATA_WIDTH : integer := 8);
	port(
	--input 
	--data,clk,rst 
			rxd : in	  std_logic;
			di : in std_logic_vector(DATA_WIDTH - 1 downto 0);
			sys_clk_50MHZ,rst_p  : in std_logic;
			en : in std_logic;
	--output 
	--rxd,data
		   txd : out  std_logic;
			do : out std_logic_vector(DATA_WIDTH - 1 downto 0)
	);
end component;

component trans_4_to_8
	port(
			i : in std_logic_vector(3 downto 0);
			o : out std_logic_vector(7 downto 0)
	);
end component;

component debounce_circut 
	port(
		sys_clk,reset : std_logic;
		sw : in std_logic;
		db_level,db_tick : out std_logic
	);
end component;


	signal data_8 : std_logic_vector(7 downto 0);
	signal en_r : std_logic;
begin
	--uut_keydwn_check : keydwn_check port map(en,sys_clk_50MHZ,en_r);
	uut_uart_core : MyUartCore  port map(rxd,data_8,sys_clk_50MHZ,rst_p,en_r,txd,led);
	uut_trans_4_to_8 : trans_4_to_8 port map(sw,data_8);
	uut_debounce : debounce_circut port map(sys_clk_50MHZ,rst_p,en,open,en_r);

end Behavioral;