transfer.vhd

串口通讯源码

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:09:02 11/06/2012 
-- Design Name: 
-- Module Name:    transfer - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity transfer is
	port(
		sys_clk_50MHZ : in std_logic;
		txd : out std_logic;
		dbin : in std_logic_vector(7 downto 0);
		bclk : in std_logic;
		rst_p : in std_logic;
		TBE	: inout std_logic 	:= '1';			--Transfer Bus Empty
		WR		: in  std_logic					--Write Strobe
	);
end transfer;

architecture Behavioral of transfer is

	--发送状态机
	type tstate is (
		sttIdle,			--Idle state
		sttTransfer,	--Move data into shift register
		sttShift			--Shift out data
		);
	--发送总线空闲状态机
	type TBEstate is (
		stbeIdle,	--Idle state
		stbeSetTBE,	--Set the transfer bus empty
		stbeWaitLoad,	--wait load
		stbeWaitWrite	--wait write 
		);
		
	--Transfer holding register
	signal tfReg	:  std_logic_vector(7 downto 0);
	----Transfer shift register
	signal tfSReg  :  std_logic_vector(10 downto 0) := "11111111111";
	--used to delay in transfer
	signal tfCtr	:  std_logic_vector(3 downto 0)	:= "0000";
	--Transfering Clock
	signal tClk		:  std_logic;
	signal load		:  std_logic := '0';
	signal shift	:  std_logic := '0';
	--Current state in the Transfer state machine
	signal sttCur  :  tstate := sttIdle;
	--Next state in the Transfer staet machine	
	signal sttNext :  tstate;		
	--Current state in the transfer state empty machine
	signal stbeCur :  TBEstate := stbeIdle;
	--Next state in the Transfer state empty machine 	
	signal stbeNext:  TBEstate;		
	signal rClkDiv : std_logic_vector(3 downto 0) := "0000";
	signal tClkRST : std_logic := '0';
	signal par : std_logic := '0';

begin

	tfReg <= dbin;
	par <=  not ( ((tfSReg(0) xor tfSReg(1)) xor (tfSReg(2) xor tfSReg(3))) xor ((tfSReg(4) xor tfSReg(5)) xor (tfSReg(6) xor tfSReg(7))) );
	--产生发送时钟
	--set up clock divide for tClk
	process (bclk)	  								     
	begin
		if (bclk = '1' and bclk'event) then
			rClkDiv <= rClkDiv + 1;
		end if;
	end process;
	
	tClk <= rclkDiv(3);
	
	--set up a counter based on tClk
	process (tClk, tClkRST)	 							
	begin
		if (tClk = '1' and tClk'event) then
			if tClkRST = '1' then
				tfCtr <= "0000";
			else
				tfCtr <= tfCtr +1;
			end if;
		end if;
	end process;
	
	--  Transfer State Machine--
	process (tClk, rst_p)
	begin
		if (tClk = '1' and tClk'Event) then
			if RST_p = '1' then
				sttCur <= sttIdle;
			else
				sttCur <= sttNext;
			end if;
		end if;
	end process;
	
	--  This process generates the sequence of steps needed transfer the data--
	process (sttCur, tfCtr, tfReg, TBE, tclk)
	begin   	   
		case sttCur is
			--空闲
			when sttIdle =>
				tClkRST <= '0';
				shift <= '0';
				load <= '0';
				if TBE = '1' then
					sttNext <= sttIdle;
				else
					sttNext <= sttTransfer;
				end if;	
				
			--发送状态
			when sttTransfer =>	
				shift <= '0';
				load <= '1';
				tClkRST <= '1';		
				sttNext <= sttShift;
				
			--移位状态
			when sttShift =>
				shift <= '1';
				load <= '0';
				tClkRST <= '0';
				if tfCtr = "1100" then
					sttNext <= sttIdle;
				else
					sttNext <= sttShift;
				end if;
		end case;
	end process;	
	
	--TBE State Machine--
	process (sys_clk_50MHZ, rst_p)
	begin
		if sys_clk_50MHZ = '1' and sys_clk_50MHZ'Event then
			if rst_p = '1' then
				stbeCur <= stbeIdle;
			else
				stbeCur <= stbeNext;
			end if;
		end if;
	end process;
	--This process gererates the sequence of events needed to control the TBE flag--
	process (stbeCur, sys_clk_50MHZ, WR, DBIN, load)
	begin

		case stbeCur is

			when stbeIdle =>
				TBE <= '1';
				if WR = '1' then
					stbeNext <= stbeSetTBE;
				else
					stbeNext <= stbeIdle;
				end if;
			
			when stbeSetTBE =>
				TBE <= '0';
				if load = '1' then
					stbeNext <= stbeWaitLoad;
				else
					stbeNext <= stbeSetTBE;
				end if;
			
			when stbeWaitLoad =>
				if load = '0' then
					stbeNext <= stbeWaitWrite;
				else
					stbeNext <= stbeWaitLoad;
				end if;

			when stbeWaitWrite =>
				if WR = '0' then 
					stbeNext <= stbeIdle;
				else
					stbeNext <= stbeWaitWrite;
				end if;
			end case;
	end process;
	
	--This process loads and shifts out the transfer shift register--
	process (load, shift, tClk, tfSReg)
	begin
		TXD <= tfsReg(0);
		if tClk = '1' and tClk'Event then
			if load = '1' then
				tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
			end if;
			if shift = '1' then			  
				tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
			end if;
		end if;
	end process;

	
end Behavioral;