keydwn_check.vhd

串口通讯源码

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:04:11 11/10/2012 
-- Design Name: 
-- Module Name:    keydwn_check - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--entity keydwn_check is
--	port(
--		en_i : in std_logic;
--		en_o : out std_logic;
--		sys_clk_50MHZ : in std_logic;
--		rst_p : in std_logic
--	);
--end keydwn_check;
--
--architecture Behavioral of keydwn_check is
--	signal count : std_logic_vector(31 downto 0) := (others => '0');
--begin
--	process(sys_clk_50MHZ,rst_p)
--	begin
--		if(rst_p = '1')then
--			count <= (others => '0');
--		elsif(sys_clk_50MHZ'event and sys_clk_50MHZ = '1')then
--			if(count = x"4c4b40")then--5000000
--				count <= (others => '0');
--			else
--				count <= count  + '1';
--			end if;
--		end if;
--	end process;
--	
--	process(count,en_i)
--	begin
--		if(count = x"4c4b40")then
--			en_o <= en_i;
--		else
--			en_o <= '0';
--		end if;
--	end process;
--
--
--end Behavioral;

entity keydwn_check is
     Port ( 
				btn_0 : in  STD_LOGIC;
            clk : in  STD_LOGIC;
            en : out  STD_LOGIC
			 );
 end keydwn_check;
 
architecture Behavioral of keydwn_check is

 constant CNTR_MAX : std_logic_vector(19 downto 0) := (others => '1');
 signal btn0_cntr : std_logic_vector(19 downto 0) := (others => '0');
 signal btn0_reg : std_logic := '0';
 signal en_r : std_logic := '0';
 
begin
	 btn0_debounce_process : process (CLK)
	 begin
	  if (rising_edge(CLK)) then
		if (btn0_cntr = CNTR_MAX) then
		 btn0_reg <= not(btn0_reg);
		end if;
	  end if;
	 end process;
	 
	 btn0_counter_process : process (CLK)
	 begin
	  if (rising_edge(CLK)) then
		if ((btn0_reg = '1') xor (btn_0 = '1')) then
		 if (btn0_cntr = CNTR_MAX) then
		  btn0_cntr <= (others => '0');
		 else
		  btn0_cntr <= btn0_cntr + 1;
		 end if;
		else
		 btn0_cntr <= (others => '0');
		end if;
	  end if;
	 end process;
	 
	 process(btn0_reg)
	 begin
	  if rising_edge(btn0_reg) then
		en_r  <= not en_r;
	  end if;
	 end process;
	 
	 en <= '1' when en_r ='1' else
	       '0'; 
	 
end Behavioral;