hdpdeps.ref

串口通讯源码

V3 30
FL "D:/Project/Xilinx Project/My_Own/MyUart/baud_gen.vhd" 2012/11/06.22:02:39 P.28xd
EN work/baud_gen 1352726406 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/baud_gen.vhd" \
      PB ieee/std_logic_1164 1341906176 PB ieee/STD_LOGIC_UNSIGNED 1341906179
AR work/baud_gen/Behavioral 1352726407 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/baud_gen.vhd" EN work/baud_gen 1352726406
FL "D:/Project/Xilinx Project/My_Own/MyUart/debounce_circut.vhd" 2012/11/12.21:19:16 P.28xd
EN work/debounce_circut 1352726416 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/debounce_circut.vhd" \
      PB ieee/std_logic_1164 1341906176 PB ieee/STD_LOGIC_UNSIGNED 1341906179
AR work/debounce_circut/Behavioral 1352726417 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/debounce_circut.vhd" \
      EN work/debounce_circut 1352726416
FL "D:/Project/Xilinx Project/My_Own/MyUart/keydwn_check.vhd" 2012/11/10.23:30:02 P.28xd
EN work/keydwn_check 1352561414 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/keydwn_check.vhd" \
      PB ieee/std_logic_1164 1341906176 PB ieee/STD_LOGIC_UNSIGNED 1341906179
AR work/keydwn_check/Behavioral 1352561415 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/keydwn_check.vhd" \
      EN work/keydwn_check 1352561414
FL "D:/Project/Xilinx Project/My_Own/MyUart/MyUartCore.vhd" 2012/11/12.21:19:06 P.28xd
EN work/MyUartCore 1352726412 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/MyUartCore.vhd" \
      PB ieee/std_logic_1164 1341906176
AR work/MyUartCore/Behavioral 1352726413 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/MyUartCore.vhd" \
      EN work/MyUartCore 1352726412 CP baud_gen CP transfer CP recv
FL "D:/Project/Xilinx Project/My_Own/MyUart/recv.vhd" 2012/11/10.21:23:02 P.28xd
EN work/recv 1352726410 FL "D:/Project/Xilinx Project/My_Own/MyUart/recv.vhd" \
      PB ieee/std_logic_1164 1341906176 PB ieee/STD_LOGIC_UNSIGNED 1341906179
AR work/recv/Behavioral 1352726411 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/recv.vhd" EN work/recv 1352726410
FL "D:/Project/Xilinx Project/My_Own/MyUart/top.vhd" 2012/11/12.21:13:34 P.28xd
EN work/top 1352726418 FL "D:/Project/Xilinx Project/My_Own/MyUart/top.vhd" \
      PB ieee/std_logic_1164 1341906176
AR work/top/Behavioral 1352726419 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/top.vhd" EN work/top 1352726418 \
      CP MyUartCore CP trans_4_to_8 CP debounce_circut
FL "D:/Project/Xilinx Project/My_Own/MyUart/transfer.vhd" 2012/11/10.21:21:27 P.28xd
EN work/transfer 1352726408 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/transfer.vhd" \
      PB ieee/std_logic_1164 1341906176 PB ieee/STD_LOGIC_UNSIGNED 1341906179
AR work/transfer/Behavioral 1352726409 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/transfer.vhd" EN work/transfer 1352726408
FL "D:/Project/Xilinx Project/My_Own/MyUart/trans_4_to_8.vhd" 2012/11/12.21:19:06 P.28xd
EN work/trans_4_to_8 1352726414 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/trans_4_to_8.vhd" \
      PB ieee/std_logic_1164 1341906176
AR work/trans_4_to_8/Behavioral 1352726415 \
      FL "D:/Project/Xilinx Project/My_Own/MyUart/trans_4_to_8.vhd" \
      EN work/trans_4_to_8 1352726414