📄 top_map.mrp
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Release 14.2 Map P.28xd (nt64)Xilinx Mapping Report File for Design 'top'Design Information------------------Command Line : map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off
-c 100 -o top_map.ncd top.ngd top.pcf Target Device : xc3s500eTarget Package : fg320Target Speed : -4Mapper Version : spartan3e -- $Revision: 1.55 $Mapped Date : Mon Nov 12 21:20:43 2012Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization: Total Number Slice Registers: 106 out of 9,312 1% Number used as Flip Flops: 105 Number used as Latches: 1 Number of 4 input LUTs: 140 out of 9,312 1%Logic Distribution: Number of occupied Slices: 102 out of 4,656 2% Number of Slices containing only related logic: 102 out of 102 100% Number of Slices containing unrelated logic: 0 out of 102 0% *See NOTES below for an explanation of the effects of unrelated logic. Total Number of 4 input LUTs: 175 out of 9,312 1% Number used as logic: 139 Number used as a route-thru: 35 Number used as Shift registers: 1 The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. Number of bonded IOBs: 17 out of 232 7% Number of BUFGMUXs: 2 out of 24 8%Average Fanout of Non-Clock Nets: 2.82Peak Memory Usage: 277 MBTotal REAL time to MAP completion: 6 secs Total CPU time to MAP completion: 3 secs NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Timing ReportSection 11 - Configuration String InformationSection 12 - Control Set InformationSection 13 - Utilization by HierarchySection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Term | Strength | Rate | | | Delay |+---------------------------------------------------------------------------------------------------------------------------------------------------------+| en | IBUF | INPUT | LVTTL | | | | | PULLDOWN | 0 / 0 || led<0> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | 0 / 0 || led<1> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | 0 / 0 || led<2> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | 0 / 0 || led<3> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | 0 / 0 || led<4> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | 0 / 0 || led<5> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | 0 / 0 || led<6> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | 0 / 0 || led<7> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | 0 / 0 || rst_p | IBUF | INPUT | LVTTL | | | | | PULLDOWN | 0 / 0 || rxd | IBUF | INPUT | LVTTL | | | | | | 0 / 0 || sw<0> | IBUF | INPUT | LVTTL | | | | | PULLUP | 0 / 0 || sw<1> | IBUF | INPUT | LVTTL | | | | | PULLUP | 0 / 0 || sw<2> | IBUF | INPUT | LVTTL | | | | | PULLUP | 0 / 0 || sw<3> | IBUF | INPUT | LVTTL | | | | | PULLUP | 0 / 0 || sys_clk_50MHZ | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 || txd | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | 0 / 0 |+---------------------------------------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status------------------------------- No Partitions were found in this design.-------------------------------Area Group Information---------------------- No area groups were found in this design.----------------------Section 10 - Timing Report--------------------------This design was not run using timing mode.Section 11 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 12 - Control Set Information------------------------------------No control set information for this architecture.Section 13 - Utilization by Hierarchy-------------------------------------Use the "-detail" map option to print out the Utilization by Hierarchy section.⌨️ 快捷键说明
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