trans_4_to_8.vhd

来自「串口通讯源码」· VHDL 代码 · 共 61 行

----------------------------------------------------------------------------------
-- Company: Xidian University Computer
-- Engineer: jefby
-- 
-- Create Date:    20:56:53 11/10/2012 
-- Design Name:    MyUart
-- Module Name:    trans_4_to_8 - Behavioral 
-- Project Name: 
-- Target Devices: Spartan-3E
-- Tool versions: 
-- Description: 将4位键盘输入值转换为16进制的ASCII值
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity trans_4_to_8 is
	port(
		i : in std_logic_vector(3 downto 0);
		o : out std_logic_vector(7 downto 0)
	);
end trans_4_to_8;

architecture Behavioral of trans_4_to_8 is

begin
	o <= x"3" & i when i = x"0" else
		  x"3" & i when i = x"1" else
		  x"3" & i when i = x"2" else
		  x"3" & i when i = x"3" else
		  x"3" & i when i = x"4" else
		  x"3" & i when i = x"5" else
		  x"3" & i when i = x"6" else
		  x"3" & i when i = x"7" else
		  x"3" & i when i = x"8" else
		  x"3" & i when i = x"9" else
		  x"41" when i = x"a" else
		  x"42" when i = x"b" else
		  x"43" when i = x"c" else
		  x"44" when i = x"d" else
		  x"45" when i = x"e" else
		  x"46" when i = x"f" else
		  x"00" ;
end Behavioral;