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串口通讯源码

-------------------------------------------+-----------------------------------------+-------+
Clock Signal                               | Clock buffer(FF name)                   | Load  |
-------------------------------------------+-----------------------------------------+-------+
sys_clk_50MHZ                              | BUFGP                                   | 58    |
uut_uart_core/uut_baud_gen/bclk_pad1       | BUFG                                    | 32    |
uut_uart_core/uut_transfer/rClkDiv_3       | NONE(uut_uart_core/uut_transfer/tfCtr_3)| 16    |
uut_uart_core/uut_transfer/stbeCur_FSM_FFd1| NONE(uut_uart_core/uut_transfer/TBE)    | 1     |
-------------------------------------------+-----------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
rst_p                              | IBUF                   | 57    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.845ns (Maximum Frequency: 127.470MHz)
   Minimum input arrival time before clock: 5.974ns
   Maximum output required time after clock: 5.744ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'sys_clk_50MHZ'
  Clock period: 7.845ns (frequency: 127.470MHz)
  Total number of paths / destination ports: 3050 / 79
-------------------------------------------------------------------------
Delay:               7.845ns (Levels of Logic = 25)
  Source:            uut_debounce/q_reg_0 (FF)
  Destination:       uut_debounce/state_reg_FSM_FFd1 (FF)
  Source Clock:      sys_clk_50MHZ rising
  Destination Clock: sys_clk_50MHZ rising

  Data Path: uut_debounce/q_reg_0 to uut_debounce/state_reg_FSM_FFd1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.591   0.622  uut_debounce/q_reg_0 (uut_debounce/q_reg_0)
     LUT1:I0->O            1   0.704   0.000  uut_debounce/Msub_q_next_addsub0000_cy<0>_rt (uut_debounce/Msub_q_next_addsub0000_cy<0>_rt)
     MUXCY:S->O            1   0.464   0.000  uut_debounce/Msub_q_next_addsub0000_cy<0> (uut_debounce/Msub_q_next_addsub0000_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<1> (uut_debounce/Msub_q_next_addsub0000_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<2> (uut_debounce/Msub_q_next_addsub0000_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<3> (uut_debounce/Msub_q_next_addsub0000_cy<3>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<4> (uut_debounce/Msub_q_next_addsub0000_cy<4>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<5> (uut_debounce/Msub_q_next_addsub0000_cy<5>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<6> (uut_debounce/Msub_q_next_addsub0000_cy<6>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<7> (uut_debounce/Msub_q_next_addsub0000_cy<7>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<8> (uut_debounce/Msub_q_next_addsub0000_cy<8>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<9> (uut_debounce/Msub_q_next_addsub0000_cy<9>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<10> (uut_debounce/Msub_q_next_addsub0000_cy<10>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<11> (uut_debounce/Msub_q_next_addsub0000_cy<11>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<12> (uut_debounce/Msub_q_next_addsub0000_cy<12>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<13> (uut_debounce/Msub_q_next_addsub0000_cy<13>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<14> (uut_debounce/Msub_q_next_addsub0000_cy<14>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<15> (uut_debounce/Msub_q_next_addsub0000_cy<15>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<16> (uut_debounce/Msub_q_next_addsub0000_cy<16>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<17> (uut_debounce/Msub_q_next_addsub0000_cy<17>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<18> (uut_debounce/Msub_q_next_addsub0000_cy<18>)
     MUXCY:CI->O           0   0.059   0.000  uut_debounce/Msub_q_next_addsub0000_cy<19> (uut_debounce/Msub_q_next_addsub0000_cy<19>)
     XORCY:CI->O           1   0.804   0.424  uut_debounce/Msub_q_next_addsub0000_xor<20> (uut_debounce/q_next_addsub0000<20>)
     LUT4:I3->O            1   0.704   0.000  uut_debounce/db_tick3_wg_lut<5> (uut_debounce/db_tick3_wg_lut<5>)
     MUXCY:S->O            3   0.864   0.535  uut_debounce/db_tick3_wg_cy<5> (uut_debounce/db_tick3_wg_cy<5>)
     LUT4:I3->O            1   0.704   0.000  uut_debounce/state_reg_FSM_FFd1-In11 (uut_debounce/state_reg_FSM_FFd1-In)
     FDC:D                     0.308          uut_debounce/state_reg_FSM_FFd1
    ----------------------------------------
    Total                      7.845ns (6.264ns logic, 1.581ns route)
                                       (79.8% logic, 20.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'uut_uart_core/uut_baud_gen/bclk_pad1'
  Clock period: 5.134ns (frequency: 194.780MHz)
  Total number of paths / destination ports: 201 / 60
-------------------------------------------------------------------------
Delay:               5.134ns (Levels of Logic = 3)
  Source:            uut_uart_core/uut_recv/ctr_2 (FF)
  Destination:       uut_uart_core/uut_recv/ctr_3 (FF)
  Source Clock:      uut_uart_core/uut_baud_gen/bclk_pad1 rising
  Destination Clock: uut_uart_core/uut_baud_gen/bclk_pad1 rising

  Data Path: uut_uart_core/uut_recv/ctr_2 to uut_uart_core/uut_recv/ctr_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.591   0.706  uut_uart_core/uut_recv/ctr_2 (uut_uart_core/uut_recv/ctr_2)
     LUT3_D:I0->O          3   0.704   0.610  uut_uart_core/uut_recv/ctRst111 (uut_uart_core/uut_recv/strCur_cmp_eq0000)
     LUT3:I1->O            1   0.704   0.000  uut_uart_core/uut_recv/ctRst1 (uut_uart_core/uut_recv/ctRst1)
     MUXF5:I1->O           4   0.321   0.587  uut_uart_core/uut_recv/ctRst_f5 (uut_uart_core/uut_recv/ctRst)
     FDR:R                     0.911          uut_uart_core/uut_recv/ctr_0
    ----------------------------------------
    Total                      5.134ns (3.231ns logic, 1.903ns route)
                                       (62.9% logic, 37.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'uut_uart_core/uut_transfer/rClkDiv_3'
  Clock period: 3.840ns (frequency: 260.417MHz)
  Total number of paths / destination ports: 71 / 31
-------------------------------------------------------------------------
Delay:               3.840ns (Levels of Logic = 1)
  Source:            uut_uart_core/uut_transfer/sttCur_FSM_FFd2 (FF)
  Destination:       uut_uart_core/uut_transfer/tfSReg_9 (FF)
  Source Clock:      uut_uart_core/uut_transfer/rClkDiv_3 rising
  Destination Clock: uut_uart_core/uut_transfer/rClkDiv_3 rising

  Data Path: uut_uart_core/uut_transfer/sttCur_FSM_FFd2 to uut_uart_core/uut_transfer/tfSReg_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             11   0.591   1.108  uut_uart_core/uut_transfer/sttCur_FSM_FFd2 (uut_uart_core/uut_transfer/sttCur_FSM_FFd2)
     LUT2:I0->O           10   0.704   0.882  uut_uart_core/uut_transfer/tfSReg_not00011 (uut_uart_core/uut_transfer/tfSReg_not0001)
     FDE:CE                    0.555          uut_uart_core/uut_transfer/tfSReg_0
    ----------------------------------------
    Total                      3.840ns (1.850ns logic, 1.990ns route)
                                       (48.2% logic, 51.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'uut_uart_core/uut_baud_gen/bclk_pad1'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              4.681ns (Levels of Logic = 2)
  Source:            rst_p (PAD)
  Destination:       uut_uart_core/uut_recv/rdReg_7 (FF)
  Destination Clock: uut_uart_core/uut_baud_gen/bclk_pad1 rising

  Data Path: rst_p to uut_uart_core/uut_recv/rdReg_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            64   1.218   1.447  rst_p_IBUF (rst_p_IBUF)
     LUT3:I0->O            8   0.704   0.757  uut_uart_core/uut_recv/rdReg_and00001 (uut_uart_core/uut_recv/rdReg_and0000)
     FDE:CE                    0.555          uut_uart_core/uut_recv/rdReg_0
    ----------------------------------------
    Total                      4.681ns (2.477ns logic, 2.204ns route)
                                       (52.9% logic, 47.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_clk_50MHZ'
  Total number of paths / destination ports: 279 / 48
-------------------------------------------------------------------------
Offset:              5.974ns (Levels of Logic = 23)
  Source:            en (PAD)
  Destination:       uut_debounce/q_reg_20 (FF)
  Destination Clock: sys_clk_50MHZ rising

  Data Path: en to uut_debounce/q_reg_20
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            27   1.218   1.340  en_IBUF (en_IBUF)
     LUT3:I1->O            1   0.704   0.420  uut_debounce/q_load1 (uut_debounce/q_load)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<0> (uut_debounce/Mcount_q_reg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<1> (uut_debounce/Mcount_q_reg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<2> (uut_debounce/Mcount_q_reg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<3> (uut_debounce/Mcount_q_reg_cy<3>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<4> (uut_debounce/Mcount_q_reg_cy<4>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<5> (uut_debounce/Mcount_q_reg_cy<5>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<6> (uut_debounce/Mcount_q_reg_cy<6>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<7> (uut_debounce/Mcount_q_reg_cy<7>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<8> (uut_debounce/Mcount_q_reg_cy<8>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<9> (uut_debounce/Mcount_q_reg_cy<9>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<10> (uut_debounce/Mcount_q_reg_cy<10>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<11> (uut_debounce/Mcount_q_reg_cy<11>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<12> (uut_debounce/Mcount_q_reg_cy<12>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<13> (uut_debounce/Mcount_q_reg_cy<13>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<14> (uut_debounce/Mcount_q_reg_cy<14>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<15> (uut_debounce/Mcount_q_reg_cy<15>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<16> (uut_debounce/Mcount_q_reg_cy<16>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<17> (uut_debounce/Mcount_q_reg_cy<17>)
     MUXCY:CI->O           1   0.059   0.000  uut_debounce/Mcount_q_reg_cy<18> (uut_debounce/Mcount_q_reg_cy<18>)
     MUXCY:CI->O           0   0.059   0.000  uut_debounce/Mcount_q_reg_cy<19> (uut_debounce/Mcount_q_reg_cy<19>)
     XORCY:CI->O           1   0.804   0.000  uut_debounce/Mcount_q_reg_xor<20> (uut_debounce/Mcount_q_reg20)
     FDCE:D                    0.308          uut_debounce/q_reg_20
    ----------------------------------------
    Total                      5.974ns (4.214ns logic, 1.760ns route)
                                       (70.5% logic, 29.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'uut_uart_core/uut_transfer/rClkDiv_3'
  Total number of paths / destination ports: 29 / 9
-------------------------------------------------------------------------
Offset:              4.408ns (Levels of Logic = 3)
  Source:            sw<2> (PAD)
  Destination:       uut_uart_core/uut_transfer/tfSReg_7 (FF)
  Destination Clock: uut_uart_core/uut_transfer/rClkDiv_3 rising

  Data Path: sw<2> to uut_uart_core/uut_transfer/tfSReg_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   1.218   0.808  sw_2_IBUF (sw_2_IBUF)
     LUT3:I0->O            4   0.704   0.666  data_8<4>1 (data_8<4>)
     LUT3:I1->O            1   0.704   0.000  uut_uart_core/uut_transfer/tfSReg_mux0000<7>1 (uut_uart_core/uut_transfer/tfSReg_mux0000<7>)
     FDE:D                     0.308          uut_uart_core/uut_transfer/tfSReg_7
    ----------------------------------------
    Total                      4.408ns (2.934ns logic, 1.474ns route)
                                       (66.6% logic, 33.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'uut_uart_core/uut_transfer/rClkDiv_3'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.310ns (Levels of Logic = 1)
  Source:            uut_uart_core/uut_transfer/tfSReg_0 (FF)
  Destination:       txd (PAD)
  Source Clock:      uut_uart_core/uut_transfer/rClkDiv_3 rising

  Data Path: uut_uart_core/uut_transfer/tfSReg_0 to txd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.591   0.447  uut_uart_core/uut_transfer/tfSReg_0 (uut_uart_core/uut_transfer/tfSReg_0)
     OBUF:I->O                 3.272          txd_OBUF (txd)
    ----------------------------------------
    Total                      4.310ns (3.863ns logic, 0.447ns route)
                                       (89.6% logic, 10.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'uut_uart_core/uut_baud_gen/bclk_pad1'
  Total number of paths / destination ports: 16 / 8
-------------------------------------------------------------------------
Offset:              5.744ns (Levels of Logic = 2)
  Source:            uut_uart_core/uut_recv/RDA (FF)
  Destination:       led<7> (PAD)
  Source Clock:      uut_uart_core/uut_baud_gen/bclk_pad1 rising

  Data Path: uut_uart_core/uut_recv/RDA to led<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             1   0.591   0.420  uut_uart_core/uut_recv/RDA (uut_uart_core/uut_recv/RDA)
     INV:I->O              8   0.704   0.757  uut_uart_core/uut_recv/RDA_inv1_INV_0 (uut_uart_core/uut_recv/RDA_inv)
     OBUFT:T->O                3.272          led_7_OBUFT (led<7>)
    ----------------------------------------
    Total                      5.744ns (4.567ns logic, 1.177ns route)
                                       (79.5% logic, 20.5% route)

=========================================================================


Total REAL time to Xst completion: 13.00 secs
Total CPU time to Xst completion: 12.61 secs
 
--> 

Total memory usage is 276024 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    4 (   0 filtered)
Number of infos    :    2 (   0 filtered)