top.syr

串口通讯源码

	inferred   2 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred  11 D-type flip-flop(s).
	inferred   1 Xor(s).
Unit <transfer> synthesized.


Synthesizing Unit <recv>.
    Related source file is "D:/Project/Xilinx Project/My_Own/MyUart/recv.vhd".
    Found finite state machine <FSM_3> for signal <strCur>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 7                                              |
    | Inputs             | 3                                              |
    | Outputs            | 4                                              |
    | Clock              | bclk                      (rising_edge)        |
    | Reset              | rst_p                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | stridle                                        |
    | Power Up State     | stridle                                        |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <RDA>.
    Found 8-bit tristate buffer for signal <dbout>.
    Found 4-bit up counter for signal <ctr>.
    Found 4-bit up counter for signal <dataCtr>.
    Found 8-bit register for signal <rdReg>.
    Found 10-bit register for signal <rdSReg>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred  19 D-type flip-flop(s).
	inferred   8 Tristate(s).
Unit <recv> synthesized.


Synthesizing Unit <MyUartCore>.
    Related source file is "D:/Project/Xilinx Project/My_Own/MyUart/MyUartCore.vhd".
Unit <MyUartCore> synthesized.


Synthesizing Unit <top>.
    Related source file is "D:/Project/Xilinx Project/My_Own/MyUart/top.vhd".
Unit <top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 16x8-bit ROM                                          : 1
# Adders/Subtractors                                   : 1
 21-bit subtractor                                     : 1
# Counters                                             : 6
 21-bit down counter                                   : 1
 32-bit up counter                                     : 1
 4-bit up counter                                      : 4
# Registers                                            : 5
 1-bit register                                        : 2
 10-bit register                                       : 1
 11-bit register                                       : 1
 8-bit register                                        : 1
# Latches                                              : 1
 1-bit latch                                           : 1
# Tristates                                            : 1
 8-bit tristate buffer                                 : 1
# Xors                                                 : 1
 1-bit xor8                                            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <uut_uart_core/uut_recv/strCur/FSM> on signal <strCur[1:2]> with gray encoding.
---------------------------
 State         | Encoding
---------------------------
 stridle       | 00
 streightdelay | 01
 strgetdata    | 11
 strcheckstop  | 10
---------------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <uut_uart_core/uut_transfer/stbeCur/FSM> on signal <stbeCur[1:2]> with gray encoding.
---------------------------
 State         | Encoding
---------------------------
 stbeidle      | 00
 stbesettbe    | 01
 stbewaitload  | 11
 stbewaitwrite | 10
---------------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <uut_uart_core/uut_transfer/sttCur/FSM> on signal <sttCur[1:2]> with user encoding.
-------------------------
 State       | Encoding
-------------------------
 sttidle     | 00
 stttransfer | 01
 sttshift    | 10
-------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <uut_debounce/state_reg/FSM> on signal <state_reg[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 zero  | 00
 wait0 | 10
 one   | 11
 wait1 | 01
-------------------
WARNING:Xst:1293 - FF/Latch <tfSReg_10> has a constant value of 1 in block <uut_transfer>. This FF/Latch will be trimmed during the optimization process.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 4
# ROMs                                                 : 1
 16x8-bit ROM                                          : 1
# Adders/Subtractors                                   : 1
 21-bit subtractor                                     : 1
# Counters                                             : 6
 21-bit down counter                                   : 1
 32-bit up counter                                     : 1
 4-bit up counter                                      : 4
# Registers                                            : 31
 Flip-Flops                                            : 31
# Latches                                              : 1
 1-bit latch                                           : 1
# Xors                                                 : 1
 1-bit xor8                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch <tfSReg_10> has a constant value of 1 in block <transfer>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <top> ...

Optimizing unit <debounce_circut> ...

Optimizing unit <transfer> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 2.

Final Macro Processing ...

Processing Unit <top> :
	Found 3-bit shift register for signal <uut_uart_core/uut_recv/rdSReg_7>.
Unit <top> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 104
 Flip-Flops                                            : 104
# Shift Registers                                      : 1
 3-bit shift register                                  : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 17

Cell Usage :
# BELS                             : 344
#      GND                         : 1
#      INV                         : 27
#      LUT1                        : 32
#      LUT2                        : 45
#      LUT3                        : 19
#      LUT3_D                      : 1
#      LUT4                        : 52
#      MUXCY                       : 85
#      MUXF5                       : 7
#      VCC                         : 1
#      XORCY                       : 74
# FlipFlops/Latches                : 106
#      FD                          : 3
#      FDC                         : 34
#      FDCE                        : 23
#      FDE                         : 26
#      FDR                         : 14
#      FDRE                        : 4
#      FDRS                        : 1
#      LD_1                        : 1
# Shift Registers                  : 1
#      SRL16E                      : 1
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 16
#      IBUF                        : 7
#      OBUF                        : 1
#      OBUFT                       : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s500efg320-4 

 Number of Slices:                      109  out of   4656     2%  
 Number of Slice Flip Flops:            106  out of   9312     1%  
 Number of 4 input LUTs:                177  out of   9312     1%  
    Number used as logic:               176
    Number used as Shift registers:       1
 Number of IOs:                          17
 Number of bonded IOBs:                  17  out of    232     7%  
 Number of GCLKs:                         2  out of     24     8%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------