top.syr

串口通讯源码

Release 14.2 - xst P.28xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.37 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.39 secs
 
--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/Project/Xilinx Project/My_Own/MyUart/baud_gen.vhd" in Library work.
Architecture behavioral of Entity baud_gen is up to date.
Compiling vhdl file "D:/Project/Xilinx Project/My_Own/MyUart/transfer.vhd" in Library work.
Architecture behavioral of Entity transfer is up to date.
Compiling vhdl file "D:/Project/Xilinx Project/My_Own/MyUart/recv.vhd" in Library work.
Architecture behavioral of Entity recv is up to date.
Compiling vhdl file "D:/Project/Xilinx Project/My_Own/MyUart/MyUartCore.vhd" in Library work.
Entity <myuartcore> compiled.
Entity <myuartcore> (Architecture <behavioral>) compiled.
Compiling vhdl file "D:/Project/Xilinx Project/My_Own/MyUart/trans_4_to_8.vhd" in Library work.
Entity <trans_4_to_8> compiled.
Entity <trans_4_to_8> (Architecture <behavioral>) compiled.
Compiling vhdl file "D:/Project/Xilinx Project/My_Own/MyUart/debounce_circut.vhd" in Library work.
Entity <debounce_circut> compiled.
Entity <debounce_circut> (Architecture <behavioral>) compiled.
Compiling vhdl file "D:/Project/Xilinx Project/My_Own/MyUart/top.vhd" in Library work.
Entity <top> compiled.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <top> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <MyUartCore> in library <work> (architecture <behavioral>) with generics.
	DATA_WIDTH = 8

Analyzing hierarchy for entity <trans_4_to_8> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <debounce_circut> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <baud_gen> in library <work> (architecture <behavioral>) with generics.
	BAUD_VALUE = 9600

Analyzing hierarchy for entity <transfer> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <recv> in library <work> (architecture <behavioral>) with generics.
	DATA_WIDTH = 8


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> in library <work> (Architecture <behavioral>).
WARNING:Xst:753 - "D:/Project/Xilinx Project/My_Own/MyUart/top.vhd" line 98: Unconnected output port 'db_level' of component 'debounce_circut'.
Entity <top> analyzed. Unit <top> generated.

Analyzing generic Entity <MyUartCore> in library <work> (Architecture <behavioral>).
	DATA_WIDTH = 8
Entity <MyUartCore> analyzed. Unit <MyUartCore> generated.

Analyzing generic Entity <baud_gen> in library <work> (Architecture <behavioral>).
	BAUD_VALUE = 9600
Entity <baud_gen> analyzed. Unit <baud_gen> generated.

Analyzing Entity <transfer> in library <work> (Architecture <behavioral>).
Entity <transfer> analyzed. Unit <transfer> generated.

Analyzing generic Entity <recv> in library <work> (Architecture <behavioral>).
	DATA_WIDTH = 8
Entity <recv> analyzed. Unit <recv> generated.

Analyzing Entity <trans_4_to_8> in library <work> (Architecture <behavioral>).
Entity <trans_4_to_8> analyzed. Unit <trans_4_to_8> generated.

Analyzing Entity <debounce_circut> in library <work> (Architecture <behavioral>).
Entity <debounce_circut> analyzed. Unit <debounce_circut> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <trans_4_to_8>.
    Related source file is "D:/Project/Xilinx Project/My_Own/MyUart/trans_4_to_8.vhd".
    Found 16x8-bit ROM for signal <o>.
    Summary:
	inferred   1 ROM(s).
Unit <trans_4_to_8> synthesized.


Synthesizing Unit <debounce_circut>.
    Related source file is "D:/Project/Xilinx Project/My_Own/MyUart/debounce_circut.vhd".
    Found finite state machine <FSM_0> for signal <state_reg>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 10                                             |
    | Inputs             | 2                                              |
    | Outputs            | 5                                              |
    | Clock              | sys_clk                   (rising_edge)        |
    | Reset              | reset                     (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | zero                                           |
    | Power Up State     | zero                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 21-bit subtractor for signal <q_next$addsub0000> created at line 62.
    Found 21-bit down counter for signal <q_reg>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 Adder/Subtractor(s).
Unit <debounce_circut> synthesized.


Synthesizing Unit <baud_gen>.
    Related source file is "D:/Project/Xilinx Project/My_Own/MyUart/baud_gen.vhd".
    Found 1-bit register for signal <bclk_pad>.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <baud_gen> synthesized.


Synthesizing Unit <transfer>.
    Related source file is "D:/Project/Xilinx Project/My_Own/MyUart/transfer.vhd".
    Found finite state machine <FSM_1> for signal <sttCur>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 5                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | tClk                      (rising_edge)        |
    | Reset              | rst_p                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | sttidle                                        |
    | Power Up State     | sttidle                                        |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_2> for signal <stbeCur>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 8                                              |
    | Inputs             | 2                                              |
    | Outputs            | 4                                              |
    | Clock              | sys_clk_50MHZ             (rising_edge)        |
    | Reset              | rst_p                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | stbeidle                                       |
    | Power Up State     | stbeidle                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 1-bit latch for signal <TBE>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 1-bit xor8 for signal <par$xor0000> created at line 85.
    Found 4-bit up counter for signal <rClkDiv>.
    Found 4-bit up counter for signal <tfCtr>.
    Found 11-bit register for signal <tfSReg>.
    Summary: