async_fifo.v.txt

the verilog model of async_fifo.

//**********************************************************************************************// 
// $Id: async_fifo_v0.0 2001/4/19 18:36:31 $ 
//**********************************************************************************************// 
//-- Filename : async_fifo_v0_0.v 
//-- Module : async_fifo 
//-- Author : mail007. 
//-- : [e-mail] 
//-- Creation : April. 19th, 2001 
//-- Description: This file contains the verilog behavioral model for the asynchornous fifo . 
//-- Compatible xilinx inc. Coregen async_fifo_v3_0 ver 
//-- Reference : fifoctlr_ic.v 
`timescale 1 ns/10ps 


module async_fifo (READ_CLOCK_IN, WRITE_CLOCK_IN, READ_ENABLE_IN, 
WRITE_ENABLE_IN, FIFO_GSR_IN, WRITE_DATA_IN, 
READ_DATA_OUT, FULL_OUT, EMPTY_OUT); 

parameter DATA_WIDTH = 8; 
parameter FIFO_DEPTH = 8 
parameter ADDR_WIDTH = 3; 

input READ_CLOCK_IN, WRITE_CLOCK_IN; 
input READ_ENABLE_IN, WRITE_ENABLE_IN; 
input FIFO_GSR_IN; 
input [DATA_WIDTH-1 : 0] WRITE_DATA_IN; 
output [DATA_WIDTH-1 : 0] READ_DATA_OUT; 
output FULL_OUT, EMPTY_OUT; 

wire read_enable = READ_ENABLE_IN; 
wire write_enable = WRITE_ENABLE_IN; 
wire fifo_gsr = FIFO_GSR_IN; 
wire [DATA_WIDTH-1 : 0] write_data = WRITE_DATA_IN; 
wire read_allow, write_allow; 
wire emptyg, almostemptyg, fullg, almostfullg; 

reg [DATA_WIDTH-1 : 0] fifo_ram [FIFO_DEPTH-1 : 0]; 
reg [ADDR_WIDTH-1 : 0] read_addr, write_addr; 
reg [ADDR_WIDTH-1 : 0] write_addrgray, write_nextgray; 
reg [ADDR_WIDTH-1 : 0] read_addrgray, read_nextgray, read_lastgray; 


reg [DATA_WIDTH-1 : 0] read_data; 
reg full, empty; 
assign FULL_OUT = full; 
assign EMPTY_OUT = empty; 
assign READ_DATA_OUT = read_data; 


/*---------------------------------------------------------------------\ 
* 
* Global input clock buffers are instantianted for both the read_clock 
* and the write_clock, to avoid skew problems. USE xilinx device 
* 
-----------------------------------------------------------------------*/ 

BUFGP gclkread (.I(READ_CLOCK_IN), .O(read_clock)); 
BUFGP gclkwrite (.I(WRITE_CLOCK_IN), .O(write_clock)); 

//-------------------------------------------------------------------- 
always @(posedge read_clock or posedge fifo_gsr) 
if (fifo_gsr) empty <= 'b1; 
else empty <= (emptyg || (almostemptyg && read_enable && ! empty)); 


always @(posedge write_clock or posedge fifo_gsr) 
if (fifo_gsr) full <= 'b1; 
else full <= (fullg || (almostfullg && write_enable && ! full)); 

//------------------------------------------------------------------- 
always @(posedge read_clock or posedge fifo_gsr) 
if (fifo_gsr) read_addr <= 'h0; 
else if (read_allow) read_addr <= read_addr + 1; 

always @(posedge read_clock or posedge fifo_gsr) 
if (fifo_gsr) read_nextgray <= 3'b100; //9'b100000000; 
else if (read_allow) 
read_nextgray <= {read_addr[2],(read_addr[2] ^ read_addr[1]),(read_addr[1] ^ read_addr[0])}; 
/*{ read_addr[8], (read_addr[8] ^ read_addr[7]), 
(read_addr[7] ^ read_addr[6]), (read_addr[6] ^ read_addr[5]), 
(read_addr[5] ^ read_addr[4]), (read_addr[4] ^ read_addr[3]), 
(read_addr[3] ^ read_addr[2]), (read_addr[2] ^ read_addr[1]), 
(read_addr[1] ^ read_addr[0]) };*/ 

always @(posedge read_clock or posedge fifo_gsr) 
if (fifo_gsr) read_addrgray <= 3'b101;//9'b100000001; 
else if (read_allow) read_addrgray <= read_nextgray; 

always @(posedge read_clock or posedge fifo_gsr) 
if (fifo_gsr) read_lastgray <= 3'b111;//9'b100000011; 
else if (read_allow) read_lastgray <= read_addrgray; 

//--------------------------------------------------------------------------------- 

always @(posedge write_clock or posedge fifo_gsr) 
if (fifo_gsr) write_addr <= 'h0; 
else if (write_allow) write_addr <= write_addr + 1; 

always @(posedge write_clock or posedge fifo_gsr) 
if (fifo_gsr) write_nextgray <= 3'b100;//9'b100000000; 
else if (write_allow) 
write_nextgray <= {write_addr[2],(write_addr[2] ^ write_addr[1]),(write_addr[1] ^ write_addr[0])}; 
/* { write_addr[8], (write_addr[8] ^ write_addr[7]), 
(write_addr[7] ^ write_addr[6]), (write_addr[6] ^ write_addr[5]), 
(write_addr[5] ^ write_addr[4]), (write_addr[4] ^ write_addr[3]), 
(write_addr[3] ^ write_addr[2]), (write_addr[2] ^ write_addr[1]), 
(write_addr[1] ^ write_addr[0]) };*/ 

always @(posedge write_clock or posedge fifo_gsr) 
if (fifo_gsr) write_addrgray <= 3'b101;//9'b100000001; 
else if (write_allow) write_addrgray <= write_nextgray; 


assign read_allow = (read_enable && ! empty); 
assign write_allow = (write_enable && ! full); 

always @(posedge write_clock) 
if(write_allow) 
fifo_ram[write_addrgray] <= write_data; 

always @(posedge read_clock or posedge fifo_gsr) 
if (fifo_gsr) 
read_data <= 8'h00; 
else if(read_allow) 
read_data <= fifo_ram[read_addrgray]; 


assign emptyg = (write_addrgray == read_addrgray) ? 1 : 0; 
assign almostemptyg = (write_addrgray == read_nextgray) ? 1 : 0; 
assign fullg = (write_addrgray == read_lastgray) ? 1 : 0; 
assign almostfullg = (write_nextgray == read_lastgray) ? 1:0; 


endmodule