performance.map.qmsg

用verilog编写的程序,用来计算误码率的,可以在编码和解码过程中用的到的!

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 21 21:11:47 2006 " "Info: Processing started: Sun May 21 21:11:47 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off performance -c performance " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off performance -c performance" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "performance.v 1 1 " "Warning: Using design file performance.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 performance " "Info: Found entity 1: performance" {  } { { "performance.v" "" { Text "C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "performance " "Info: Elaborating entity \"performance\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 performance.v(23) " "Warning (10230): Verilog HDL assignment warning at performance.v(23): truncated value with size 32 to match size of target (4)" {  } { { "performance.v" "" { Text "C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.v" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 performance.v(24) " "Warning (10230): Verilog HDL assignment warning at performance.v(24): truncated value with size 32 to match size of target (4)" {  } { { "performance.v" "" { Text "C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "BER\[7\]~reg0 data_in GND " "Warning: Reduced register \"BER\[7\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "performance.v" "" { Text "C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.v" 7 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "BER\[6\]~reg0 data_in GND " "Warning: Reduced register \"BER\[6\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "performance.v" "" { Text "C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.v" 7 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "BER\[5\]~reg0 data_in GND " "Warning: Reduced register \"BER\[5\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "performance.v" "" { Text "C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.v" 7 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "BER\[4\]~reg0 data_in GND " "Warning: Reduced register \"BER\[4\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "performance.v" "" { Text "C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.v" 7 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "BER\[4\] GND " "Warning: Pin \"BER\[4\]\" stuck at GND" {  } { { "performance.v" "" { Text "C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "BER\[5\] GND " "Warning: Pin \"BER\[5\]\" stuck at GND" {  } { { "performance.v" "" { Text "C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "BER\[6\] GND " "Warning: Pin \"BER\[6\]\" stuck at GND" {  } { { "performance.v" "" { Text "C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "BER\[7\] GND " "Warning: Pin \"BER\[7\]\" stuck at GND" {  } { { "performance.v" "" { Text "C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "28 " "Info: Implemented 28 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 21 21:11:49 2006 " "Info: Processing ended: Sun May 21 21:11:49 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}