performance.map.rpt

用verilog编写的程序,用来计算误码率的,可以在编码和解码过程中用的到的!

; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                         ;
+----------------------------------+-----------------+-----------+-------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path                                                  ;
+----------------------------------+-----------------+-----------+-------------------------------------------------------------------------------+
; performance.v                    ; yes             ; Other     ; C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.v ;
+----------------------------------+-----------------+-----------+-------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 16    ;
;     -- Combinational with no register       ; 4     ;
;     -- Register only                        ; 4     ;
;     -- Combinational with a register        ; 8     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 3     ;
;     -- 3 input functions                    ; 0     ;
;     -- 2 input functions                    ; 7     ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 1     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 13    ;
;     -- arithmetic mode                      ; 3     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 4     ;
;     -- asynchronous clear/load mode         ; 8     ;
;                                             ;       ;
; Total registers                             ; 12    ;
; Total logic cells in carry chains           ; 4     ;
; I/O pins                                    ; 12    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 12    ;
; Total fan-out                               ; 66    ;
; Average fan-out                             ; 2.36  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                     ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |performance               ; 16 (16)     ; 12           ; 0           ; 0            ; 0       ; 0         ; 0         ; 12   ; 0            ; 4 (4)        ; 4 (4)             ; 8 (8)            ; 4 (4)           ; 0 (0)      ; |performance        ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 12    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 8     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/Administrator/桌面/已调试/performance/performance.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sun May 21 21:11:47 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off performance -c performance
Warning: Using design file performance.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: performance
Info: Elaborating entity "performance" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at performance.v(23): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at performance.v(24): truncated value with size 32 to match size of target (4)
Warning: Reduced register "BER[7]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "BER[6]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "BER[5]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "BER[4]~reg0" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "BER[4]" stuck at GND
    Warning: Pin "BER[5]" stuck at GND
    Warning: Pin "BER[6]" stuck at GND
    Warning: Pin "BER[7]" stuck at GND
Info: Implemented 28 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 8 output pins
    Info: Implemented 16 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Processing ended: Sun May 21 21:11:49 2006
    Info: Elapsed time: 00:00:03