performance.fit.summary

用verilog编写的程序,用来计算误码率的,可以在编码和解码过程中用的到的!

Fitter Status : Successful - Sun May 21 21:12:04 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : performance
Top-level Entity Name : performance
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 16 / 10,570 ( < 1 % )
Total pins : 12 / 336 ( 4 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )