performance.tan.rpt

用verilog编写的程序,用来计算误码率的,可以在编码和解码过程中用的到的!

; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[2] ; BER[2]~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.781 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[1]     ; i[2]        ; clk        ; clk      ; None                        ; None                      ; 0.670 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[1]     ; i[3]        ; clk        ; clk      ; None                        ; None                      ; 0.665 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[0]     ; i[1]        ; clk        ; clk      ; None                        ; None                      ; 0.656 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[0]     ; i[0]        ; clk        ; clk      ; None                        ; None                      ; 0.649 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[3] ; BER[3]~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.649 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[3] ; count[3]    ; clk        ; clk      ; None                        ; None                      ; 0.609 ns                ;
+-------+------------------------------------------------+----------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------+
; tsu                                                                  ;
+-------+--------------+------------+---------+-------------+----------+
; Slack ; Required tsu ; Actual tsu ; From    ; To          ; To Clock ;
+-------+--------------+------------+---------+-------------+----------+
; N/A   ; None         ; 4.082 ns   ; result  ; count[3]    ; clk      ;
; N/A   ; None         ; 4.022 ns   ; result  ; count[2]    ; clk      ;
; N/A   ; None         ; 3.962 ns   ; result  ; count[1]    ; clk      ;
; N/A   ; None         ; 3.758 ns   ; InfoSeq ; count[3]    ; clk      ;
; N/A   ; None         ; 3.698 ns   ; InfoSeq ; count[2]    ; clk      ;
; N/A   ; None         ; 3.638 ns   ; InfoSeq ; count[1]    ; clk      ;
; N/A   ; None         ; 3.553 ns   ; result  ; count[0]    ; clk      ;
; N/A   ; None         ; 3.229 ns   ; InfoSeq ; count[0]    ; clk      ;
; N/A   ; None         ; 1.160 ns   ; rst     ; BER[0]~reg0 ; clk      ;
; N/A   ; None         ; 1.160 ns   ; rst     ; BER[1]~reg0 ; clk      ;
; N/A   ; None         ; 1.160 ns   ; rst     ; BER[2]~reg0 ; clk      ;
; N/A   ; None         ; 1.160 ns   ; rst     ; BER[3]~reg0 ; clk      ;
+-------+--------------+------------+---------+-------------+----------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To     ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 6.995 ns   ; BER[0]~reg0 ; BER[0] ; clk        ;
; N/A   ; None         ; 6.989 ns   ; BER[1]~reg0 ; BER[1] ; clk        ;
; N/A   ; None         ; 6.959 ns   ; BER[2]~reg0 ; BER[2] ; clk        ;
; N/A   ; None         ; 6.958 ns   ; BER[3]~reg0 ; BER[3] ; clk        ;
+-------+--------------+------------+-------------+--------+------------+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+---------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To          ; To Clock ;
+---------------+-------------+-----------+---------+-------------+----------+
; N/A           ; None        ; -1.050 ns ; rst     ; BER[0]~reg0 ; clk      ;
; N/A           ; None        ; -1.050 ns ; rst     ; BER[1]~reg0 ; clk      ;
; N/A           ; None        ; -1.050 ns ; rst     ; BER[2]~reg0 ; clk      ;
; N/A           ; None        ; -1.050 ns ; rst     ; BER[3]~reg0 ; clk      ;
; N/A           ; None        ; -2.464 ns ; InfoSeq ; count[0]    ; clk      ;
; N/A           ; None        ; -2.788 ns ; result  ; count[0]    ; clk      ;
; N/A           ; None        ; -3.512 ns ; InfoSeq ; count[1]    ; clk      ;
; N/A           ; None        ; -3.570 ns ; InfoSeq ; count[2]    ; clk      ;
; N/A           ; None        ; -3.628 ns ; InfoSeq ; count[3]    ; clk      ;
; N/A           ; None        ; -3.836 ns ; result  ; count[1]    ; clk      ;
; N/A           ; None        ; -3.894 ns ; result  ; count[2]    ; clk      ;
; N/A           ; None        ; -3.952 ns ; result  ; count[3]    ; clk      ;
+---------------+-------------+-----------+---------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sun May 21 21:12:16 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off performance -c performance --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 369.69 MHz between source register "i[0]" and destination register "BER[3]~reg0" (period= 2.705 ns)
    Info: + Longest register to register delay is 2.539 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y9_N2; Fanout = 5; REG Node = 'i[0]'
        Info: 2: + IC(0.445 ns) + CELL(0.366 ns) = 0.811 ns; Loc. = LC_X36_Y9_N7; Fanout = 5; COMB Node = 'rtl~26'
        Info: 3: + IC(0.326 ns) + CELL(0.366 ns) = 1.503 ns; Loc. = LC_X36_Y9_N3; Fanout = 4; COMB Node = 'BER[3]~12'
        Info: 4: + IC(0.331 ns) + CELL(0.705 ns) = 2.539 ns; Loc. = LC_X36_Y9_N5; Fanout = 1; REG Node = 'BER[3]~reg0'
        Info: Total cell delay = 1.437 ns ( 56.60 % )
        Info: Total interconnect delay = 1.102 ns ( 43.40 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.858 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 12; CLK Node = 'clk'
            Info: 2: + IC(1.591 ns) + CELL(0.542 ns) = 2.858 ns; Loc. = LC_X36_Y9_N5; Fanout = 1; REG Node = 'BER[3]~reg0'
            Info: Total cell delay = 1.267 ns ( 44.33 % )
            Info: Total interconnect delay = 1.591 ns ( 55.67 % )
        Info: - Longest clock path from clock "clk" to source register is 2.858 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 12; CLK Node = 'clk'
            Info: 2: + IC(1.591 ns) + CELL(0.542 ns) = 2.858 ns; Loc. = LC_X36_Y9_N2; Fanout = 5; REG Node = 'i[0]'
            Info: Total cell delay = 1.267 ns ( 44.33 % )
            Info: Total interconnect delay = 1.591 ns ( 55.67 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "count[3]" (data pin = "result", clock pin = "clk") is 4.082 ns
    Info: + Longest pin to register delay is 6.930 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y9; Fanout = 1; PIN Node = 'result'
        Info: 2: + IC(4.064 ns) + CELL(0.183 ns) = 5.334 ns; Loc. = LC_X35_Y9_N5; Fanout = 4; COMB Node = 'always0~0'
        Info: 3: + IC(0.528 ns) + CELL(0.451 ns) = 6.313 ns; Loc. = LC_X35_Y9_N6; Fanout = 2; COMB Node = 'count[0]~50COUT1_66'
        Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 6.373 ns; Loc. = LC_X35_Y9_N7; Fanout = 2; COMB Node = 'count[1]~54COUT1'
        Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 6.433 ns; Loc. = LC_X35_Y9_N8; Fanout = 1; COMB Node = 'count[2]~58COUT1_67'
        Info: 6: + IC(0.000 ns) + CELL(0.497 ns) = 6.930 ns; Loc. = LC_X35_Y9_N9; Fanout = 2; REG Node = 'count[3]'
        Info: Total cell delay = 2.338 ns ( 33.74 % )
        Info: Total interconnect delay = 4.592 ns ( 66.26 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.858 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(1.591 ns) + CELL(0.542 ns) = 2.858 ns; Loc. = LC_X35_Y9_N9; Fanout = 2; REG Node = 'count[3]'
        Info: Total cell delay = 1.267 ns ( 44.33 % )
        Info: Total interconnect delay = 1.591 ns ( 55.67 % )
Info: tco from clock "clk" to destination pin "BER[0]" through register "BER[0]~reg0" is 6.995 ns
    Info: + Longest clock path from clock "clk" to source register is 2.858 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(1.591 ns) + CELL(0.542 ns) = 2.858 ns; Loc. = LC_X36_Y9_N1; Fanout = 1; REG Node = 'BER[0]~reg0'
        Info: Total cell delay = 1.267 ns ( 44.33 % )
        Info: Total interconnect delay = 1.591 ns ( 55.67 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.981 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y9_N1; Fanout = 1; REG Node = 'BER[0]~reg0'
        Info: 2: + IC(1.577 ns) + CELL(2.404 ns) = 3.981 ns; Loc. = PIN_Y8; Fanout = 0; PIN Node = 'BER[0]'
        Info: Total cell delay = 2.404 ns ( 60.39 % )
        Info: Total interconnect delay = 1.577 ns ( 39.61 % )
Info: th for register "BER[0]~reg0" (data pin = "rst", clock pin = "clk") is -1.050 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.858 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(1.591 ns) + CELL(0.542 ns) = 2.858 ns; Loc. = LC_X36_Y9_N1; Fanout = 1; REG Node = 'BER[0]~reg0'
        Info: Total cell delay = 1.267 ns ( 44.33 % )
        Info: Total interconnect delay = 1.591 ns ( 55.67 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.008 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 9; PIN Node = 'rst'
        Info: 2: + IC(1.961 ns) + CELL(0.183 ns) = 2.972 ns; Loc. = LC_X36_Y9_N3; Fanout = 4; COMB Node = 'BER[3]~12'
        Info: 3: + IC(0.331 ns) + CELL(0.705 ns) = 4.008 ns; Loc. = LC_X36_Y9_N1; Fanout = 1; REG Node = 'BER[0]~reg0'
        Info: Total cell delay = 1.716 ns ( 42.81 % )
        Info: Total interconnect delay = 2.292 ns ( 57.19 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun May 21 21:12:17 2006
    Info: Elapsed time: 00:00:02