📄 performance.tan.rpt
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Timing Analyzer report for performance
Sun May 21 21:12:17 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+-------------+-------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-------------+-------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.082 ns ; result ; count[3] ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 6.995 ns ; BER[0]~reg0 ; BER[0] ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -1.050 ns ; rst ; BER[3]~reg0 ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 369.69 MHz ( period = 2.705 ns ) ; i[0] ; BER[0]~reg0 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+-------------+-------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+----------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 369.69 MHz ( period = 2.705 ns ) ; i[0] ; BER[3]~reg0 ; clk ; clk ; None ; None ; 2.539 ns ;
; N/A ; 369.69 MHz ( period = 2.705 ns ) ; i[0] ; BER[2]~reg0 ; clk ; clk ; None ; None ; 2.539 ns ;
; N/A ; 369.69 MHz ( period = 2.705 ns ) ; i[0] ; BER[1]~reg0 ; clk ; clk ; None ; None ; 2.539 ns ;
; N/A ; 369.69 MHz ( period = 2.705 ns ) ; i[0] ; BER[0]~reg0 ; clk ; clk ; None ; None ; 2.539 ns ;
; N/A ; 379.22 MHz ( period = 2.637 ns ) ; i[2] ; BER[3]~reg0 ; clk ; clk ; None ; None ; 2.471 ns ;
; N/A ; 379.22 MHz ( period = 2.637 ns ) ; i[2] ; BER[2]~reg0 ; clk ; clk ; None ; None ; 2.471 ns ;
; N/A ; 379.22 MHz ( period = 2.637 ns ) ; i[2] ; BER[1]~reg0 ; clk ; clk ; None ; None ; 2.471 ns ;
; N/A ; 379.22 MHz ( period = 2.637 ns ) ; i[2] ; BER[0]~reg0 ; clk ; clk ; None ; None ; 2.471 ns ;
; N/A ; 386.70 MHz ( period = 2.586 ns ) ; i[3] ; BER[3]~reg0 ; clk ; clk ; None ; None ; 2.420 ns ;
; N/A ; 386.70 MHz ( period = 2.586 ns ) ; i[3] ; BER[2]~reg0 ; clk ; clk ; None ; None ; 2.420 ns ;
; N/A ; 386.70 MHz ( period = 2.586 ns ) ; i[3] ; BER[1]~reg0 ; clk ; clk ; None ; None ; 2.420 ns ;
; N/A ; 386.70 MHz ( period = 2.586 ns ) ; i[3] ; BER[0]~reg0 ; clk ; clk ; None ; None ; 2.420 ns ;
; N/A ; 415.28 MHz ( period = 2.408 ns ) ; i[1] ; BER[3]~reg0 ; clk ; clk ; None ; None ; 2.242 ns ;
; N/A ; 415.28 MHz ( period = 2.408 ns ) ; i[1] ; BER[2]~reg0 ; clk ; clk ; None ; None ; 2.242 ns ;
; N/A ; 415.28 MHz ( period = 2.408 ns ) ; i[1] ; BER[1]~reg0 ; clk ; clk ; None ; None ; 2.242 ns ;
; N/A ; 415.28 MHz ( period = 2.408 ns ) ; i[1] ; BER[0]~reg0 ; clk ; clk ; None ; None ; 2.242 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[0] ; count[3] ; clk ; clk ; None ; None ; 2.150 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[0] ; count[2] ; clk ; clk ; None ; None ; 2.150 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[0] ; count[1] ; clk ; clk ; None ; None ; 2.150 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[0] ; count[0] ; clk ; clk ; None ; None ; 2.150 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[2] ; count[3] ; clk ; clk ; None ; None ; 2.082 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[2] ; count[2] ; clk ; clk ; None ; None ; 2.082 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[2] ; count[1] ; clk ; clk ; None ; None ; 2.082 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[2] ; count[0] ; clk ; clk ; None ; None ; 2.082 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[3] ; count[3] ; clk ; clk ; None ; None ; 2.031 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[3] ; count[2] ; clk ; clk ; None ; None ; 2.031 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[3] ; count[1] ; clk ; clk ; None ; None ; 2.031 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[3] ; count[0] ; clk ; clk ; None ; None ; 2.031 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[1] ; count[3] ; clk ; clk ; None ; None ; 1.853 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[1] ; count[2] ; clk ; clk ; None ; None ; 1.853 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[1] ; count[1] ; clk ; clk ; None ; None ; 1.853 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[1] ; count[0] ; clk ; clk ; None ; None ; 1.853 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[1] ; count[3] ; clk ; clk ; None ; None ; 1.398 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[2] ; count[3] ; clk ; clk ; None ; None ; 1.340 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[1] ; count[2] ; clk ; clk ; None ; None ; 1.338 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[0] ; count[3] ; clk ; clk ; None ; None ; 1.334 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[0] ; count[2] ; clk ; clk ; None ; None ; 1.274 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[0] ; count[1] ; clk ; clk ; None ; None ; 1.214 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[0] ; i[3] ; clk ; clk ; None ; None ; 0.981 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[0] ; i[2] ; clk ; clk ; None ; None ; 0.979 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[2] ; count[2] ; clk ; clk ; None ; None ; 0.931 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[1] ; count[1] ; clk ; clk ; None ; None ; 0.929 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[1] ; i[1] ; clk ; clk ; None ; None ; 0.886 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[2] ; i[3] ; clk ; clk ; None ; None ; 0.878 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[3] ; i[2] ; clk ; clk ; None ; None ; 0.874 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[2] ; i[2] ; clk ; clk ; None ; None ; 0.872 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; i[3] ; i[3] ; clk ; clk ; None ; None ; 0.870 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[0] ; count[0] ; clk ; clk ; None ; None ; 0.834 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[1] ; BER[1]~reg0 ; clk ; clk ; None ; None ; 0.785 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[0] ; BER[0]~reg0 ; clk ; clk ; None ; None ; 0.784 ns ;
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