performance.map.eqn

用verilog编写的程序,用来计算误码率的,可以在编码和解码过程中用的到的!

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L3Q is BER[0]~reg0
--operation mode is normal

A1L3Q_lut_out = count[0];
A1L3Q = DFFEAS(A1L3Q_lut_out, clk, VCC, , A1L9, , , , );


--A1L5Q is BER[1]~reg0
--operation mode is normal

A1L5Q_lut_out = count[1];
A1L5Q = DFFEAS(A1L5Q_lut_out, clk, VCC, , A1L9, , , , );


--A1L7Q is BER[2]~reg0
--operation mode is normal

A1L7Q_lut_out = count[2];
A1L7Q = DFFEAS(A1L7Q_lut_out, clk, VCC, , A1L9, , , , );


--A1L10Q is BER[3]~reg0
--operation mode is normal

A1L10Q_lut_out = count[3];
A1L10Q = DFFEAS(A1L10Q_lut_out, clk, VCC, , A1L9, , , , );


--count[0] is count[0]
--operation mode is arithmetic

count[0]_lut_out = count[0] $ A1L16;
count[0] = DFFEAS(count[0]_lut_out, clk, !rst, , , A1L16, , , A1L33);

--A1L20 is count[0]~50
--operation mode is arithmetic

A1L20 = CARRY(count[0] & A1L16);


--i[3] is i[3]
--operation mode is normal

i[3]_lut_out = i[3] & (i[1] $ i[0] # !i[2]) # !i[3] & i[1] & i[0] & i[2];
i[3] = DFFEAS(i[3]_lut_out, clk, !rst, , , , , , );


--i[2] is i[2]
--operation mode is normal

i[2]_lut_out = i[1] & (i[2] $ i[0]) # !i[1] & i[2] & (i[0] # !i[3]);
i[2] = DFFEAS(i[2]_lut_out, clk, !rst, , , , , , );


--i[1] is i[1]
--operation mode is normal

i[1]_lut_out = i[1] $ i[0];
i[1] = DFFEAS(i[1]_lut_out, clk, !rst, , , , , , );


--i[0] is i[0]
--operation mode is normal

i[0]_lut_out = !i[0];
i[0] = DFFEAS(i[0]_lut_out, clk, !rst, , , , , , );


--A1L33 is rtl~26
--operation mode is normal

A1L33 = i[3] & i[2] & !i[1] & !i[0];


--A1L9 is BER[3]~12
--operation mode is normal

A1L9 = A1L33 & (!rst);


--count[1] is count[1]
--operation mode is arithmetic

count[1]_carry_eqn = A1L20;
count[1]_lut_out = count[1] $ (count[1]_carry_eqn);
count[1] = DFFEAS(count[1]_lut_out, clk, !rst, , , ~GND, , , A1L33);

--A1L22 is count[1]~54
--operation mode is arithmetic

A1L22 = CARRY(!A1L20 # !count[1]);


--count[2] is count[2]
--operation mode is arithmetic

count[2]_carry_eqn = A1L22;
count[2]_lut_out = count[2] $ (!count[2]_carry_eqn);
count[2] = DFFEAS(count[2]_lut_out, clk, !rst, , , ~GND, , , A1L33);

--A1L24 is count[2]~58
--operation mode is arithmetic

A1L24 = CARRY(count[2] & (!A1L22));


--count[3] is count[3]
--operation mode is normal

count[3]_carry_eqn = A1L24;
count[3]_lut_out = count[3] $ (count[3]_carry_eqn);
count[3] = DFFEAS(count[3]_lut_out, clk, !rst, , , ~GND, , , A1L33);


--A1L16 is always0~0
--operation mode is normal

A1L16 = InfoSeq $ result;


--~GND is ~GND
--operation mode is normal

~GND = GND;


--clk is clk
--operation mode is input

clk = INPUT();


--rst is rst
--operation mode is input

rst = INPUT();


--InfoSeq is InfoSeq
--operation mode is input

InfoSeq = INPUT();


--result is result
--operation mode is input

result = INPUT();


--BER[0] is BER[0]
--operation mode is output

BER[0] = OUTPUT(A1L3Q);


--BER[1] is BER[1]
--operation mode is output

BER[1] = OUTPUT(A1L5Q);


--BER[2] is BER[2]
--operation mode is output

BER[2] = OUTPUT(A1L7Q);


--BER[3] is BER[3]
--operation mode is output

BER[3] = OUTPUT(A1L10Q);


--BER[4] is BER[4]
--operation mode is output

BER[4] = OUTPUT(GND);


--BER[5] is BER[5]
--operation mode is output

BER[5] = OUTPUT(GND);


--BER[6] is BER[6]
--operation mode is output

BER[6] = OUTPUT(GND);


--BER[7] is BER[7]
--operation mode is output

BER[7] = OUTPUT(GND);