performance.fit.talkback.xml

用verilog编写的程序,用来计算误码率的,可以在编码和解码过程中用的到的!

<!--
This XML file (created on Sun May 21 21:12:04 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>000aeb2c524a</host_id>
	<nic_id>000aeb2c524a</nic_id>
	<cdrive_id>0c5d07ff</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_fit.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Sun May 21 21:12:05 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2399</cpu_freq>
	</cpu>
	<ram units="MB">512</ram>
	<company>liuwei</company>
</machine>
<top_file>C:/Documents and Settings/Administrator/桌面/已调试/performance/performance</top_file>
<resource_usage_summary>
	<rsc name="Total logic elements" util="1" max=" 10570 " type="int">16 </rsc>
	<rsc name="-- Combinational with no register" type="int">4</rsc>
	<rsc name="-- Register only" type="int">4</rsc>
	<rsc name="-- Combinational with a register" type="int">8</rsc>
	<rsc name="Logic element usage by number of LUT inputs" type="text"></rsc>
	<rsc name="-- 4 input functions" type="int">3</rsc>
	<rsc name="-- 3 input functions" type="int">0</rsc>
	<rsc name="-- 2 input functions" type="int">7</rsc>
	<rsc name="-- 1 input functions" type="int">4</rsc>
	<rsc name="-- 0 input functions" type="int">2</rsc>
	<rsc name="Logic elements by mode" type="text"></rsc>
	<rsc name="-- normal mode" type="int">13</rsc>
	<rsc name="-- arithmetic mode" type="int">3</rsc>
	<rsc name="-- qfbk mode" type="int">0</rsc>
	<rsc name="-- register cascade mode" type="int">0</rsc>
	<rsc name="-- synchronous clear/load mode" type="int">5</rsc>
	<rsc name="-- asynchronous clear/load mode" type="int">8</rsc>
	<rsc name="Total LABs" util="1" max=" 1057 " type="int">2 </rsc>
	<rsc name="Logic elements in carry chains" type="int">4</rsc>
	<rsc name="User inserted logic elements" type="int">0</rsc>
	<rsc name="Virtual pins" type="int">0</rsc>
	<rsc name="I/O pins" util="4" max=" 336 " type="int">12 </rsc>
	<rsc name="-- Clock pins" util="13" max=" 16 " type="int">2 </rsc>
	<rsc name="Global signals" type="int">2</rsc>
	<rsc name="M512s" util="0" max=" 94 " type="int">0 </rsc>
	<rsc name="M4Ks" util="0" max=" 60 " type="int">0 </rsc>
	<rsc name="M-RAMs" util="0" max=" 1 " type="int">0 </rsc>
	<rsc name="Total memory bits" util="0" max=" 920448 " type="int">0 </rsc>
	<rsc name="Total RAM block bits" util="0" max=" 920448 " type="int">0 </rsc>
	<rsc name="DSP block 9-bit elements" util="0" max=" 48 " type="int">0 </rsc>
	<rsc name="PLLs" util="0" max=" 6 " type="int">0 </rsc>
	<rsc name="Global clocks" util="13" max=" 16 " type="int">2 </rsc>
	<rsc name="Regional clocks" util="0" max=" 16 " type="int">0 </rsc>
	<rsc name="Fast regional clocks" util="0" max=" 8 " type="int">0 </rsc>
	<rsc name="SERDES transmitters" util="0" max=" 44 " type="int">0 </rsc>
	<rsc name="SERDES receivers" util="0" max=" 44 " type="int">0 </rsc>
	<rsc name="Maximum fan-out node" type="text">clk</rsc>
	<rsc name="Maximum fan-out" type="int">12</rsc>
	<rsc name="Highest non-global fan-out signal" type="text">~GND</rsc>
	<rsc name="Highest non-global fan-out" type="int">7</rsc>
	<rsc name="Total fan-out" type="int">70</rsc>
	<rsc name="Average fan-out" type="float">2.41</rsc>
</resource_usage_summary>
<control_signals>
	<row>
		<name>clk</name>
		<location>PIN_L2</location>
		<fan_out>12</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK11</global_line_name>
	</row>
	<row>
		<name>rst</name>
		<location>PIN_L3</location>
		<fan_out>9</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK10</global_line_name>
	</row>
</control_signals>
<non_global_high_fan_out_signals>
	<row>
		<name>BER[0]~reg0</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>BER[1]~reg0</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>BER[2]~reg0</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>BER[3]~reg0</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>count[0]</name>
		<fan_out>2</fan_out>
	</row>
	<row>
		<name>count[0]~50</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>count[0]~50COUT1_66</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>i[3]</name>
		<fan_out>3</fan_out>
	</row>
	<row>
		<name>i[2]</name>
		<fan_out>3</fan_out>
	</row>
	<row>
		<name>i[1]</name>
		<fan_out>4</fan_out>
	</row>
</non_global_high_fan_out_signals>
<interconnect_usage_summary>
	<rsc name="Local routing interconnects" util="1" max=" 10570 " type="int">10 </rsc>
	<rsc name="LUT chains" util="0" max=" 9513 " type="int">0 </rsc>
	<rsc name="R4 interconnects" util="1" max=" 62520 " type="int">2 </rsc>
	<rsc name="R8 interconnects" util="1" max=" 10410 " type="int">6 </rsc>
	<rsc name="R24 interconnects" util="0" max=" 2280 " type="int">0 </rsc>
	<rsc name="C4 interconnects" util="1" max=" 31320 " type="int">1 </rsc>
	<rsc name="C8 interconnects" util="1" max=" 7272 " type="int">4 </rsc>
	<rsc name="C16 interconnects" util="1" max=" 2286 " type="int">3 </rsc>
	<rsc name="I/O buses" util="0" max=" 208 " type="int">0 </rsc>
	<rsc name="Fast regional clocks" util="0" max=" 8 " type="int">0 </rsc>
	<rsc name="Global clocks" util="13" max=" 16 " type="int">2 </rsc>
	<rsc name="Regional clocks" util="0" max=" 16 " type="int">0 </rsc>
	<rsc name="DIFFIOCLKs" util="0" max=" 16 " type="int">0 </rsc>
	<rsc name="DQS-8 I/O buses" util="0" max=" 16 " type="int">0 </rsc>
	<rsc name="DQS-32 I/O buses" util="0" max=" 4 " type="int">0 </rsc>
	<rsc name="DQS bus muxes" util="0" max=" 56 " type="int">0 </rsc>
	<rsc name="Direct links" util="1" max=" 44740 " type="int">8 </rsc>
</interconnect_usage_summary>
<mep_data>
	<command_line>quartus_fit --read_settings_files=off --write_settings_files=off performance -c performance</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<fitter_settings>
	<row>
		<option>Device</option>
		<setting>AUTO</setting>
	</row>
	<row>
		<option>SignalProbe signals routed during normal compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Router Timing Optimization Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Placement Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Router Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Optimize Hold Timing</option>
		<setting>IO Paths and Minimum TPD Paths</setting>
		<default_value>IO Paths and Minimum TPD Paths</default_value>
	</row>
	<row>
		<option>Optimize Fast-Corner Timing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Optimize Timing</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize IOC Register Placement for Timing</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit to One Fitting Attempt</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Final Placement Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Aggressive Routability Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Initial Placement Seed</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>Slow Slew Rate</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>PCI I/O</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Weak Pull-Up Resistor</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Enable Bus-Hold Circuitry</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Global Memory Control Signals</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Packed Registers -- Stratix/Stratix GX</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Auto Delay Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Merge PLLs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Perform Physical Synthesis for Combinational Logic</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform Register Duplication</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform Register Retiming</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform Asynchronous Signal Pipelining</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Fitter Effort</option>
		<setting>Auto Fit</setting>
		<default_value>Auto Fit</default_value>
	</row>
	<row>
		<option>Physical Synthesis Effort Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Logic Cell Insertion - Logic Duplication</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Auto Register Duplication</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Global Clock</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Register Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
</fitter_settings>
<fitter_device_options>
	<row>
		<option>Enable user-supplied start-up clock (CLKUSR)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide reset (DEV_CLRn)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide output enable (DEV_OE)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable INIT_DONE output</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Configuration scheme</option>
		<setting>Passive Serial</setting>
	</row>
	<row>
		<option>Error detection CRC</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Reserve Data[0] pin after configuration</option>
		<setting>As input tri-stated</setting>
	</row>
	<row>
		<option>Reserve all unused pins</option>
		<setting>As output driving ground</setting>
	</row>
	<row>
		<option>Base pin-out file on sameframe device</option>
		<setting>Off</setting>
	</row>
</fitter_device_options>
<input_pins>
	<row>
		<name>InfoSeq</name>
		<pin__>U9</pin__>
		<i_o_bank>7</i_o_bank>
		<x_coordinate>36</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>5</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>clk</name>
		<pin__>L2</pin__>
		<i_o_bank>5</i_o_bank>
		<x_coordinate>53</x_coordinate>
		<y_coordinate>19</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>12</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>yes</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>result</name>
		<pin__>Y9</pin__>
		<i_o_bank>7</i_o_bank>
		<x_coordinate>36</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>rst</name>
		<pin__>L3</pin__>
		<i_o_bank>5</i_o_bank>
		<x_coordinate>53</x_coordinate>
		<y_coordinate>19</y_coordinate>
		<cell_number>1</cell_number>
		<combinational_fan_out>9</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>yes</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
</input_pins>
<output_pins>
	<row>
		<name>BER[0]</name>
		<pin__>Y8</pin__>
		<i_o_bank>7</i_o_bank>
		<x_coordinate>36</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>3</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>BER[1]</name>
		<pin__>P8</pin__>
		<i_o_bank>7</i_o_bank>
		<x_coordinate>36</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>