performance.sim.talkback.xml

用verilog编写的程序,用来计算误码率的,可以在编码和解码过程中用的到的!

<!--
This XML file (created on Sun May 21 21:13:43 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>000aeb2c524a</host_id>
	<nic_id>000aeb2c524a</nic_id>
	<cdrive_id>0c5d07ff</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_sim.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Sun May 21 21:13:44 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2399</cpu_freq>
	</cpu>
	<ram units="MB">512</ram>
	<company>liuwei</company>
</machine>
<top_file>C:/Documents and Settings/Administrator/桌面/已调试/performance/performance</top_file>
<mep_data>
	<command_line>quartus_sim --read_settings_files=on --write_settings_files=off performance -c performance</command_line>
</mep_data>
<simulator_settings>
	<row>
		<option>Simulation mode</option>
		<setting>Timing</setting>
		<default_value>Timing</default_value>
	</row>
	<row>
		<option>Start time</option>
		<setting units="ns">0</setting>
		<default_value units="ns">0</default_value>
	</row>
	<row>
		<option>Add pins automatically to simulation output waveforms</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Check outputs</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Report simulation coverage</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Detect setup and hold time violations</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Detect glitches</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Automatically save/load simulation netlist</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Disable timing delays in Timing Simulation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Signal Activity File</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Group bus channels in simulation results</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Preserve fewer signal transitions to reduce memory requirements</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Overwrite Waveform Inputs With Simulation Outputs</option>
		<setting>Off</setting>
	</row>
</simulator_settings>
<simulator_summary>
	<simulation_start_time>0 ps</simulation_start_time>
	<simulation_end_time>5.0 us</simulation_end_time>
	<simulation_netlist_size>28 nodes</simulation_netlist_size>
	<simulation_coverage>     63.64 %</simulation_coverage>
	<total_number_of_transitions>295</total_number_of_transitions>
	<family>Stratix</family>
	<device>EP1S10F484C5</device>
</simulator_summary>
<compile_id>63E01E60</compile_id>
</talkback>