📄 ipk.vhd
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; use ieee.std_logic_arith.all; use work.pack.all; entity ipk_comparator is port ( clk, en_ipk, en_clr : in std_logic; result : in std_logic_vector(7 downto 0); pp : out std_logic_vector(7 downto 0) ); end ipk_comparator; architecture behavioral of ipk_comparator is type state_type is (state0, state1,state2); type reg_type is record state : state_type; count : std_logic_vector(5 downto 0); ipos : std_logic_vector(5 downto 0); peak : std_logic_vector(7 downto 0); ipk : std_logic_vector(9 downto 0); threshold_1 : std_logic_vector(15 downto 0); threshold : std_logic_vector(7 downto 0); end record; signal r,rin: reg_type; begin process (en_ipk, r, result, en_clr) variable v : reg_type; begin v := r; case r.state is when state0 => if en_clr = '0' then v.state := state1; end if; when state1 => if en_clr = '0' then v.state := state2; end if; v.count := "000000"; v.peak := (others => '0'); v.ipos := (others => '0'); v.ipk := (others => '0'); v.threshold_1:= result * "01001110"; v.threshold := v.threshold_1(15 downto 8); when state2 => if en_clr = '0' then if r.count = "000000" then v.count := r.count + 1; v.peak := result; v.ipos := "000101"; elsif r.count = "011001" then if r.peak < result then v.peak := result; v.ipos := "011110"; end if; if v.peak > v.threshold then v.ipk := v.ipos * "0100"; else v.ipk := (others => '0'); end if; else v.count := r.count + 1; if v.peak < result then v.peak := result; v.ipos := r.count + 5; end if; end if; end if; end case; if en_ipk = '0' then v.state := state0; v.count := "000000"; v.peak := (others => '0'); v.ipos := (others => '0'); v.ipk := (others => '0'); v.threshold_1 := (others => '0'); v.threshold := (others => '0'); end if; rin <= v; pp <= v.ipk(7 downto 0); end process; process (rin, clk) begin if clk'event and clk = '1' then r <= rin; end if; end process;end behavioral;
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