comparator.vhd

来自「使用vhdl编写的一段程序。 主要功能是声音周期计算」· VHDL 代码 · 共 83 行

  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_signed.all;
  use ieee.std_logic_arith.all;
  use work.pack.all;

  entity comparator is
    port (
      en_comparator, rst, clk  : in  std_logic;
      en_peak                  : in  std_logic;
      sample1                  : in output_type;
      sample2                  : in output_type;
      peak                     : out output_type
      );
  end comparator;

architecture behavioral of comparator is
  
    type reg_type is record
                        p1    : std_logic_vector(17 downto 0);
                        p2    : std_logic_vector(17 downto 0);
                        p_temp: std_logic_vector(15 downto 0);
                        samp1 : std_logic_vector(17 downto 0);
                        samp2 : std_logic_vector(17 downto 0);
                      end record;
    
    signal r, rin : reg_type;
  begin  
    process (r, rst, sample1, sample2, en_peak, en_comparator)
      variable v : reg_type;
    begin  -- process
      v := r;
      if sample1 > 0 then
          v.samp1 := sample1 * "01";
      else
          v.samp1 := sample1 * "11";
      end if;
      if v.p1 > v.samp1 then
          v.p1 := v.p1;
      else
          v.p1 := v.samp1;
      end if;
      
      if sample2 > 0 then
          v.samp2 := sample2 * "01";
      else
          v.samp2 := sample2 * "11";
      end if;
      if v.p2 > v.samp2 then
          v.p2 := v.p2;
      else
          v.p2 := v.samp2;
      end if;
      
      if en_peak = '1' then
          if v.p1 > v.p2 then
              v.p_temp := v.p2(15 downto 0);
          else
              v.p_temp := v.p1(15 downto 0);
          end if;
      end if;
     
    if rst = '0' or en_comparator = '0' then
        v.p1     := (others => '0');
        v.p2     := (others => '0');
        v.p_temp := (others => '0');
        v.samp1  := (others => '0');
        v.samp2  := (others => '0');
    end if;

      rin  <= v;
      peak <= v.p_temp;
      
    end process;

    process (rin, clk)
    begin  
      if clk'event and clk='1' then
        r <= rin;
      end if;
    end process;
end behavioral;