control.vhd

使用vhdl编写的一段程序。 主要功能是声音周期计算

library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.pack.all;

  entity ctrl is
    port (
      clk, rst : in  std_logic;
      enable   : out en_type);
  end ctrl;

  architecture behavioral of ctrl is

    type state_type is (state0, state1, state2);      
    type reg_type is record
                        state : state_type;
                        count : std_logic_vector(15 downto 0);
                        mult1 : std_logic_vector(5 downto 0);
                        mult2 : std_logic_vector(5 downto 0);
                      end record;
    
    signal r, rin : reg_type;

  begin  -- behavioral

    process (r, rst)
      variable v : reg_type;
    begin  -- process
      v := r;
      
      enable.addr           <= "000000";
      enable.en_FIR         <= '0';
      enable.en_decimate    <= '0';
      enable.en_FIFO        <= '0';
      enable.en_comparator  <= '0';
      enable.en_peak        <= '0';
      enable.en_clipper     <= '0';
      enable.cs             <= '1';
      enable.oe             <= '1';
      enable.en_acc         <= '0';
      enable.en_ipk         <= '0';
      enable.en_clr         <= '1';
      enable.recycle        <= '0';
      enable.en_write       <= '0';
      enable.en_read        <= '0';
      enable.clk_FIFO       <= '0';

      case r.state is
          
        when state0 => 
                    enable.en_FIR         <= '1';
                    enable.en_read        <= '1';
                    enable.en_comparator  <= '1';
                if r.count = "0000000001001111" then
                    v.state := state1;
                    v.count := (others => '0');
                    enable.en_peak <= '1';
                else
                    v.state := state0;
                    v.count := v.count + 1;
                end if;
                if r.count(1 downto 0) = "00" then
                    enable.en_decimate    <= '1';
                    enable.clk_FIFO       <= '1';
                elsif r.count(1 downto 0) = "01" then 
                    enable.clk_FIFO        <= '1'; 
                end if;
                        
        when state1 => 
                    enable.addr           <= r.count(5 downto 0);
                    enable.en_clipper     <= '1';
                    enable.en_FIFO        <= '1';
                    enable.cs             <= '0';
                    enable.oe             <= '1';
                if r.count = "0000000000111011" then
                    v.state := state2;
                    v.count := (others => '0');
                else
                    v.state := state1;
                    v.count := v.count + 1;
                    if r.count > "0000000000010011" then
                    enable.recycle <= '1';
                    end if;
                end if;
     
         when state2 => 
                    enable.addr           <= r.count(5 downto 0);
                    enable.cs             <= '0';
                    enable.oe             <= '0';
                    enable.en_acc         <= '1';
                    enable.en_ipk         <= '1';
                  if r.count = "0000000000000001" then
                         v.count := (others => '0');
                         enable.addr <= r.mult1 + r.mult2;
                         if  r.mult2 = "000000" and r.mult2 + r.mult1 = "111011" then
                              v.mult1 := "000000";
                              v.mult2 := "000101";
                              v.state := state2;
                         elsif r.mult2 = "011111" and r.mult2 + r.mult1 = "011111" then
                              v.mult1 := "000000";
                              v.mult2 := "000000";
                              v.state := state0;
                         elsif r.mult2 + r.mult1 = "111011" then
                              v.mult2 := v.mult2+1;
                              v.mult1 := "000000";
                              v.state := state2;
                         else
                              v.mult1 := v.mult1+1;
                              v.state := state2;
                         end if;
                         
                  else
                        v.count := r.count + 1;
                        v.state := state2;
                        enable.addr <= r.mult1;
                        if r.mult1 = "000000" then
                             enable.en_clr <= '0';
                        end if;
                        if r.mult2 = "011111" and r.mult2 + r.mult1 = "011111" then
                              enable.en_write <= '1';
                        end if;
                  end if;

      end case;

      if rst = '0' then
        v.state := state0;
        v.mult1 := (others => '0');
        v.mult2 := (others => '0');
        v.count := (others => '0');
      end if;

      rin <= v;
    end process;

    process (clk, rin)
    begin  -- process
      if clk = '1' and clk'event then
        r <= rin;
      end if;
    end process;

  end behavioral;