fifo.vhd

使用vhdl编写的一段程序。 主要功能是声音周期计算

  library ieee;
  use ieee.std_logic_1164.all;
  use work.pack.all;
  use work.components_pack.all;

  entity FIFO is
    port (
      clk, rst, en_FIFO          : in  std_logic;
      recycle, clk_FIFO          : in  std_logic;
      x                          : in  output_type;
      y2                         : out output_type;
      y3                         : out output_type);
  end FIFO;

  architecture behavioral of FIFO is

    signal d        : data_type;           -- Registers for direct form
    signal data     : output_type;
    signal clk_1    : std_logic;
    
  begin  -- structural  
    process (recycle, x, d, en_FIFO, clk, clk_FIFO)
    begin
        if recycle = '1' then
            data <= d(60);
        else
            data <= x;
        end if; 
        
	    	if en_FIFO = '1' then
            clk_1 <= clk;
            else
            clk_1 <= clk_FIFO;
        end if;
       
end process;

      d(0)     <= data;
      y2       <= d(40);
      y3       <= d(60);
      
      FIFO : for i in 0 to 59 generate
        ff : dff
          generic map (
            w => DA_WIDTH)
          port map (
            clk => clk_1,
            rst => rst,
            d   => d(i),
            q   => d(i+1));
              
      end generate FIFO;

end architecture;