decimate.vhd

来自「使用vhdl编写的一段程序。 主要功能是声音周期计算」· VHDL 代码 · 共 38 行

--Decimate with factor 4
  library ieee;
  use ieee.std_logic_1164.all;
  use work.pack.all;
  use work.components_pack.all;  

  entity decimate is
    port (
      rst, en_decimate, clk : in  std_logic;
      dac                   : in output_type;
      sample                : out output_type);
  end decimate;

architecture behavioral of decimate is
    signal r, rin : output_type;
  begin  
   process (rst, dac, en_decimate, r)
       variable v : output_type;
    begin  -- process
            v := r;
        if en_decimate = '1' then
            v := dac;
        end if;
        if rst = '0' then
            v := (others => '0');
        end if;
            rin <= v;
            sample <= v;
    end process;
    
    process (clk, rin)
      begin  -- process
         if clk = '1' and clk'event then 
           r <= rin;
         end if;
    end process;

end behavioral;