📄 centerclipper.vhd
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; use ieee.std_logic_arith.all; use work.components_pack.all; use work.pack.all; entity clipper is port ( en_clipper, clk, en_peak : in std_logic; y3 : in output_type; peak : in output_type; data_in : out std_logic_vector(1 downto 0)); end clipper;architecture behavioral of clipper is type reg_type is record CL : std_logic_vector(23 downto 0); y : std_logic_vector(24 downto 0); d : std_logic_vector(26 downto 0); temp : std_logic_vector(1 downto 0); end record; signal r, rin : reg_type; begin process (en_clipper, y3, peak, r, en_peak) variable v : reg_type; begin v := r; v.y := y3 * "010000000"; if en_peak = '1' then v.CL := peak * "01010111"; end if; if v.y > 0 then if v.y > v.CL then v.temp := "01"; else v.temp := "00"; end if; elsif v.y = 0 then v.temp := "00"; else v.d := v.y * "11"; if v.d > v.CL then v.temp := "11"; else v.temp := "00"; end if; end if; if en_clipper = '0' and en_peak = '0' then v.CL := (others => '0'); end if; if en_clipper = '0' then v.y := (others => '0'); v.d := (others => '0'); v.temp := (others => '0'); end if; rin <= v; data_in <= v.temp; end process; process (clk, rin) begin -- process if clk'event and clk = '1' then r <= rin; end if; end process; end behavioral;
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