ram.vhd

来自「使用vhdl编写的一段程序。 主要功能是声音周期计算」· VHDL 代码 · 共 49 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity ram is
 generic(width: integer := 2;   -- used to change the memory data's width
    depth: integer := 6);   -- used to change the memery address' width during 
             -- instantiation.
 port(
  clk      : in std_logic;                           --clock
  addr     : in std_logic_vector(depth - 1 downto 0); --address bus
  cs       : in std_logic;       --chip select
  oe       : in std_logic;       --output enable
             --high for write
             --low for read
  data_in  : in std_logic_vector(width - 1 downto 0);
  data_out : out std_logic_vector(width - 1 downto 0) --read data bus
  );
end ram;



architecture Behavioral of ram is



type ram is array(2 ** depth - 1 downto 0) of std_logic_vector(width - 1 downto 0);
signal ram1  : ram; 



begin
 process(clk)
 begin
  if(clk'event and clk = '1') then
   if(cs = '0') then 
    if(oe = '0') then
     data_out <= ram1(conv_integer(addr));
    else
     ram1(conv_integer(addr)) <= data_in;  
    end if;
   end if;
  end if;
 end process;
end Behavioral;