fir.vhd

来自「使用vhdl编写的一段程序。 主要功能是声音周期计算」· VHDL 代码 · 共 80 行

  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_signed.all;
  use ieee.std_logic_arith.all;
  use work.pack.all;
  use work.components_pack.all;

  entity FIR is
    port (
      clk, rst, en_FIR : in  std_logic;
      x                : in  input_type;
      y                : out output_type);
  end FIR;

  architecture behavioral of FIR is

    signal p       : product_type;
    signal s       : adder_type;
    signal z_d     : reg_d_type;            -- Registers for direct form
    signal temp    : add_type;
    signal clk_FIR : std_logic;
    
  begin  -- structural  
      
  process (en_FIR, clk)
    begin
           clk_FIR <= '0';
 
        if en_FIR = '1' then
            clk_FIR <= clk;
        end if;
        
    end process;
    

    
      -- Truncate to output wordlength
      temp      <= s(m);
      -- Assign input to first state register
      z_d(0)    <= x;
      y         <= temp(25 downto 10);

      first_mult : fixed_mult
        generic map (
          w            => AD_WIDTH,
          w_m          => COEFF_WIDTH,
          multiplicand => H(0))
        port map (
          input  => z_d(0),
          output => s(0)(AD_WIDTH+COEFF_WIDTH-1 downto 0));

      direct_fir : for i in 1 to M generate
        ff : dff
          generic map (
            w => AD_WIDTH)
          port map (
            clk => clk_FIR,
            rst => rst,
            d   => z_d(i-1),
            q   => z_d(i));
        mult : fixed_mult
          generic map (
            w            => AD_WIDTH,
            w_m          => COEFF_WIDTH,
            multiplicand => H(i))
          port map (
            input  => z_d(i),
            output => p(i));
        add : adder
          generic map (
            w1 => AD_WIDTH+COEFF_WIDTH+i-1,
            w2 => AD_WIDTH+COEFF_WIDTH)
          port map (
            in1    => s(i-1)(AD_WIDTH+COEFF_WIDTH+i-2 downto 0),
            in2    => p(i),
            output => s(i)(AD_WIDTH+COEFF_WIDTH+i-1 downto 0));           
      end generate direct_fir;

end architecture;