acc.vhd

使用vhdl编写的一段程序。 主要功能是声音周期计算

  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_signed.all;
  use ieee.std_logic_arith.all;
  use work.components_pack.all;

  entity acc is
    port (
      clk, rst, en_clr     : in  std_logic;
      en_acc               : in  std_logic;
      data_out             : in  std_logic_vector(1 downto 0);
      result               : out std_logic_vector(7 downto 0));
  end acc;

  architecture structural of acc is
    type state_type is (state0, state1);
    type reg_type is record
                        state  : state_type;
                        d1     : std_logic_vector(1 downto 0);
                        d2     : std_logic_vector(1 downto 0);
                        temp   : std_logic_vector(7 downto 0);
    end record; 
    signal r, rin : reg_type;
    signal p   : std_logic_vector(6 downto 0);
    signal s   : std_logic_vector(8 downto 0);
    signal z   : std_logic_vector(7 downto 0);    
    signal s_s : std_logic_vector(7 downto 0);
    signal clr : std_logic; 
  begin  -- structural  

     s_s <= s(8) & s(6 downto 0);
     
   process(data_out, en_clr, en_acc, s_s, rst, r)
          variable v : reg_type;
       begin
           v := r;
        case r.state is
            when state0 =>
               v.d1    := data_out;   
               v.state := state1;
            when state1 =>
               v.d2    := data_out;   
               v.state := state0;
        end case;
        
        if v.d1 = "00" or v.d2 = "00" then
            p <= "0000000";
        elsif v.d1 = v.d2 then
            p <= "0000001";
        else
            p <= "1111111";
        end if;

        if en_clr = '0' then
            v.temp := s_s;
        end if;
        
        if en_acc = '0' then
            v.state := state0;
            v.d1    := (others => '0');
            v.d2    := (others => '0');
        end if;
        
        if en_clr = '1' and rst = '1' then
            clr <= '1';
        else
            clr <= '0';
        end if;

         rin    <= v;
         result <= v.temp;
         
    end process;
    
    process (clk, rin)
       begin  -- process
         if clk'event and clk = '1' then
           r <= rin;
         end if;
    end process;
        
        ff : dff
          generic map (
            w => 8)
          port map (
            clk => clk,
            rst => clr,
            d   => s_s,
            q   => z);
        add : adder
          generic map (
            w1 => 8,
            w2 => 7)
          port map (
            in1    => z,
            in2    => p,
            output => s);        
            
end architecture;