📄 debounce.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DEBOUNCE IS
PORT(
CP:IN STD_LOGIC;
KEY:IN STD_LOGIC;
--DLY_OUT:OUT STD_LOGIC;
DIF_OUT:OUT STD_LOGIC
);
END ENTITY DEBOUNCE;
ARCHITECTURE A OF DEBOUNCE IS
SIGNAL SAMPLE,DLY,NDLY,DIFF:STD_LOGIC;
--SAMPLE作为取样信号可对输入KEY进行取样;
BEGIN
FREE_COUNTER:BLOCK--自由计数器&产生扫描信号;
SIGNAL Q:STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL D0:STD_LOGIC;
BEGIN
PROCESS(CP)
BEGIN
IF CP'EVENT AND CP='1' THEN
D0<=Q(17);
Q<=Q+1;
END IF;
END PROCESS;
SAMPLE<=Q(14) AND NOT D0;
END BLOCK FREE_COUNTER;
DEBOUNCE:BLOCK--执行RS触发器功能并送到输出端DLY;
SIGNAL D0,D1,S,R:STD_LOGIC;
BEGIN
PROCESS(CP)
BEGIN
IF CP'EVENT AND CP='1' THEN
IF SAMPLE='1' THEN
D1<=D0;
D0<=KEY;
S<=D1 AND D0;
R<=NOT D1 AND NOT D0;
END IF;
END IF;
END PROCESS;
DLY<=R NOR NDLY;
NDLY<=S NOR DLY;
--DLY_OUT<=DLY;
END BLOCK DEBOUNCE;
DIFFERENTIAL:BLOCK--微分电路;
SIGNAL D1,D0:STD_LOGIC;
BEGIN
PROCESS(CP)
BEGIN
IF CP'EVENT AND CP='1' THEN
D1<=D0;
D0<=DLY;
END IF;
END PROCESS;
DIFF<=D0 AND NOT D1;
END BLOCK DIFFERENTIAL;
DIF_OUT<=DIFF;
END A;
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