key12.vhd

１３键键盘的ＶＨＤＬ顶层文件

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY KEY12 IS
PORT(
	 DIN:IN STD_LOGIC_VECTOR(11 DOWNTO 0);
	 SEGOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
	 SELOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); 
	 FF1:OUT STD_LOGIC;
	 FF2:OUT STD_LOGIC;
	 CP,RST:IN STD_LOGIC
	);
END KEY12;
ARCHITECTURE A OF KEY12 IS
COMPONENT DEBOUNCE
PORT(
	 CP:IN STD_LOGIC;
	 KEY:IN STD_LOGIC;
	 DIF_OUT:OUT STD_LOGIC
	);
END COMPONENT;
COMPONENT NOTGATE
PORT(
	 D_IN:STD_LOGIC;
     DOUT:OUT STD_LOGIC
);
END COMPONENT;
COMPONENT DISPLAY 
PORT(
	 CP:IN STD_LOGIC;
	 SG:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
	 BT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	 REG:IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
SIGNAL REG:STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL FN:STD_LOGIC;
SIGNAL NOTSIGNAL:STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL DATA_OUT:STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL N:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL FF:STD_LOGIC;
SIGNAL NC:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
CONNECTION:BLOCK--连接模块;
BEGIN
GEN:FOR I IN 0 TO 11 GENERATE
UI:NOTGATE PORT MAP(D_IN=>DIN(I),DOUT=>NOTSIGNAL(I));
YI:DEBOUNCE PORT MAP(CP=>CP,KEY=>NOTSIGNAL(I),DIF_OUT=>DATA_OUT(I));
END GENERATE GEN;
X1:DISPLAY PORT MAP(CP=>CP,REG=>REG,SG=>SEGOUT,BT=>SELOUT);--显示模块;
END BLOCK CONNECTION;
FN_GENERATER:BLOCK--产生控制信号FN;
BEGIN
PROCESS(DATA_OUT,N)
BEGIN
CASE DATA_OUT IS                  --分配按键;
WHEN "000000000001"=>N<="0001";--1
WHEN "000000000010"=>N<="0010";--2
WHEN "000000000100"=>N<="0011";--3
WHEN "000000001000"=>N<="0100";--4
WHEN "000000010000"=>N<="0101";--5
WHEN "000000100000"=>N<="0110";--6
WHEN "000001000000"=>N<="0111";--7
WHEN "000010000000"=>N<="1000";--8
WHEN "000100000000"=>N<="1001";--9
WHEN "001000000000"=>N<="1100";--*功能键;
WHEN "010000000000"=>N<="0000";--0
WHEN "100000000000"=>N<="1110";--#功能键;
WHEN OTHERS=>NULL;
END CASE;
FN<=DATA_OUT(0)OR DATA_OUT(1)OR DATA_OUT(2)OR DATA_OUT(3)OR DATA_OUT(4)
OR DATA_OUT(5)OR DATA_OUT(7)OR DATA_OUT(7)OR DATA_OUT(8)OR DATA_OUT(10);
FF<=N(3)AND N(2);
END PROCESS;
END BLOCK FN_GENERATER;
FUNC_DJUGE:BLOCK--功能判断;
BEGIN
PROCESS(FF,N)
BEGIN
IF FF='1' AND N="1100"THEN
FF1<='1';
ELSIF FF='1' AND N="1110"THEN
FF2<='1';
END IF;
END PROCESS;
END BLOCK FUNC_DJUGE;--结束;
KEYINPUT:BLOCK
BEGIN
PROCESS(RST,FN,NC)
BEGIN
IF RST='0' THEN
REG<="00000000000000000000000000000000";
NC<="0000";
ELSIF FN'EVENT AND FN='1' AND NC<8 THEN
REG<=REG(27 DOWNTO 0)&N;
NC<=NC+1;
END IF;
END PROCESS;
END BLOCK KEYINPUT;
END A;