m3s003an.v

mentor UART IP verilog源码 以通过验证.

// Address Decode and Output Data Mux
// Copyright Mentor Graphics Corporation and Licensors 1999
// V1.200

// This module provides the address decoding, register file and output data muxing
// for the M16550a UART.

// Revision history:
// V1.200  - 15 June 1999
//           Changed constants from 2'b0 to 2'b00 to clear lint warning (ECN 1242)
// V1.100  - 12 May 1999
//           Baud divider register addresses decoded
// V1.000  - 26/9/96
//           Original


module m3s003an (
  CLK, MR, NCE, NRD, RD, NWR, 
  A, DI, IIR, IER, DIV, RXD,
  LOOP1, OUT1, OUT2, RTS, DTR, TSRE, THRE,
  BI, FE, PE, OE, DR, ERF, DCD, RI,
  DSR, CTS, DDCD, TERI, DDSR, DCTS, RxBlank,
  PEN, WLS0, WLS1, STB, EPS, SP, SB, NDVL,
  DA, ADD0, ADD1, ADD2, ADD4, ADD5, ADD6, ADD0B, ADD1B,
  FIFOE, IFIFOE, DMA, IDMA, RTL, RTM
  );
 

input        CLK, MR, NCE, NRD, RD, NWR;
input  [2:0] A;
input  [7:0] DI;
input  [3:0] IIR, IER;
input [15:0] DIV;
input  [7:0] RXD;
input        LOOP1, OUT1, OUT2, RTS, DTR, TSRE, THRE;
input        BI, FE, PE, OE, DR, ERF, DCD, RI;
input        DSR, CTS, DDCD, TERI, DDSR, DCTS, RxBlank;

output       PEN, WLS0, WLS1, STB, EPS, SP, SB, NDVL;
output [7:0] DA; 
output       ADD0, ADD1, ADD2, ADD4, ADD5, ADD6, ADD0B, ADD1B;
output       FIFOE, IFIFOE, DMA, IDMA, RTL, RTM;

reg       ADD0, ADD1, ADD2, ADD3, ADD4, ADD5, ADD6, ADD7;
reg [7:0] LCR, SCR, DA, IDA;
reg       WLS0, WLS1, STB, PEN, EPS, SP, SB;
reg       IFIFOE, IDMA, IRTL, IRTM, DMA, RTL, RTM;
reg [4:0] DA_reg;
reg       BLANK_ADD5, FIFOE, NDVL;
reg       ADD0B, ADD1B;


// Decode address
always @(NCE or A or LCR)
begin
  ADD0 = ~NCE & ~A[2] & ~A[1] & ~A[0] & ~LCR[7];
  ADD1 = ~NCE & ~A[2] & ~A[1] &  A[0] & ~LCR[7];
  ADD2 = ~NCE & ~A[2] &  A[1] & ~A[0];
  ADD3 = ~NCE & ~A[2] &  A[1] &  A[0];
  ADD4 = ~NCE &  A[2] & ~A[1] & ~A[0];
  ADD5 = ~NCE &  A[2] & ~A[1] &  A[0];
  ADD6 = ~NCE &  A[2] &  A[1] & ~A[0];
  ADD7 = ~NCE &  A[2] &  A[1] &  A[0];
  ADD0B = ~NCE & ~A[2] & ~A[1] & ~A[0] & LCR[7];
  ADD1B = ~NCE & ~A[2] & ~A[1] &  A[0] & LCR[7];
end

// Line Control Register
// Controls the format of the RX and TX words
always @(posedge NWR or posedge MR)
begin
  if (MR)
    LCR <= 0;
  else if (ADD3)
    LCR <= DI;
end

// Synchronise CPU channel to TX & RX Channels with a flip-flop
always @(posedge CLK)
begin
  WLS0 <= LCR[0];
  WLS1 <= LCR[1];
  STB <= LCR[2];
  PEN <= LCR[3];
  EPS <= LCR[4];
  SP <= LCR[5];
end

always @(posedge CLK or posedge MR)
  if (MR)
    SB <= 1'b0;
  else
    SB <= LCR[6];


// FIFO Control Register (write only)
//
// CPU timing domain
// Reset signals not stored as self clearing. They are dealt with in m3s008 & m3s007
always @(posedge NWR or posedge MR)
begin
  if (MR)
  begin
    IFIFOE <= 1'b0;
    IDMA <= 1'b0;
    IRTL <= 1'b0;
    IRTM <= 1'b0;
  end
  else if (ADD2 & DI[0])  // bit 0 must be set to program other bits
  begin
    IFIFOE <= DI[0]; 
    IDMA <= DI[3];
    IRTL <= DI[6];
    IRTM <= DI[7];
  end
  else if (ADD2)
  begin
    IFIFOE <= DI[0];
    IDMA <= IDMA;
    IRTL <= IRTL;
    IRTM <= IRTM;
  end
end

// Synchronise CPU, TX and RX channels
always @(posedge CLK)
begin
  FIFOE <= IFIFOE; 
  DMA <= IDMA;
  RTL <= IRTL;
  RTM <= IRTM;
end


// Scratch Register doesn't need to be synchronised since read only
// by CPU timing channel
// Note that it is not reset
always @(posedge NWR)
  if (ADD7)
    SCR[7:0] <= DI[7:0];

// Output data multiplexer
always @(ADD0 or ADD1 or ADD2 or ADD3 or ADD4 or ADD5 or ADD6 or ADD7 or
  ADD0B or ADD1B or
  RXD or IER or FIFOE or IIR or LCR or
  LOOP1 or OUT2 or OUT1 or RTS or DTR or ERF or TSRE or THRE or BI or FE or PE or OE or DR or
  DCD or RI or DSR or CTS or DDCD or TERI or DDSR or DCTS or SCR or DIV)
begin
  IDA = ({8{ADD0}} & RXD) |
        ({4'h0, ({4{ADD1}} & IER)}) |
        ({(ADD2 & FIFOE), (ADD2 & FIFOE), 2'b00, ({4{ADD2}} & IIR)}) |
        ({8{ADD3}} & LCR) |
        ({3'b000, (ADD4 & LOOP1), (ADD4 & OUT2), (ADD4 & OUT1), (ADD4 & RTS),
	  (ADD4 & DTR)}) |
        ({(ADD5 & ERF), (ADD5 & TSRE), (ADD5 & THRE), (ADD5 & BI),
	  (ADD5 & FE), (ADD5 & PE), (ADD5 & OE), (ADD5 & DR)}) |
        ({(ADD6 & DCD), (ADD6 & RI), (ADD6 & DSR), (ADD6 & CTS),
	  (ADD6 & DDCD), (ADD6 & TERI), (ADD6 & DDSR), (ADD6 & DCTS)}) |
        ({8{ADD7}} & SCR) |
        ({8{ADD0B}} & DIV[7:0]) | ({8{ADD1B}} & DIV[15:8]);
end

// Latch data on rising edge of RD so that it is frozen
// (Equates to falling edge of NRD)
//
// Blank LSR data on read-back if in M16C450 mode
always @(posedge RD)
begin
    DA[7:5] <= IDA[7:5];
    DA_reg[4:0] <= IDA[4:0];
    if (RxBlank & ADD5)
       BLANK_ADD5 <= 1'b0;
    else BLANK_ADD5 <= 1'b1;
end

always @(BLANK_ADD5 or DA_reg)
begin
    DA[4] <= DA_reg[4] & BLANK_ADD5;
    DA[3] <= DA_reg[3] & BLANK_ADD5;
    DA[2] <= DA_reg[2] & BLANK_ADD5;
    DA[1] <= DA_reg[1] & BLANK_ADD5;
    DA[0] <= DA_reg[0] & BLANK_ADD5;
end

// Generate NDVL - Output TRI-State buffer enable from 
// NCE and NRD
always @(NCE or NRD)
  NDVL = NCE | NRD;


endmodule