m3s006an.v

mentor UART IP verilog源码 以通过验证.

// Modem Output and Status Registers
// Copyright Mentor Graphics Corporation and Licensors 1999
// V1.300

// This module provides the modem output control and status registers
// for the M16550a UART.

// Revision history:
// V1.300  - 12 May 1999
//           Clock and resets renamed
// V1.2    - Corrected typing error in synchronisation for RD_DNDSRS
//	   - Added asynchronous Resets for DDCD_del, DTERI_del, DDSR_del, DCTS_del. 
//	   - 4/3/98
// V1.1    - Added Local Reset for Modem Status Delta Signals
//           10/11/97
// V1.000  - 26/9/96
//           Original

module m3s006an (
  CLK, MR, NRD, NWR, ADD4, ADD6, DI, DA,
  NDCD, TXD, SB, NRI, NDSR, NCTS,
  NOUT1, NOUT2, NRTS, NDTR, BRKTD, SOUT, LOOP1,
  OUT1, OUT2, DCD, RI, DSR, CTS, RTS, DTR,
  DDCD, DCTS, DDSR, TERI
  );

input       CLK, MR, NRD, NWR, ADD4, ADD6;
input [4:0] DI;
input [3:0] DA;
input       NDCD, TXD, SB, NRI, NDSR, NCTS;
 
output NOUT1, NOUT2, NRTS, NDTR, BRKTD, SOUT, LOOP1;
output OUT1, OUT2, DCD, RI, DSR, CTS, RTS, DTR;
output DDCD, DCTS, DDSR, TERI;

reg       LOOP1, OUT2, OUT1, RTS, DTR, WR1;
reg [1:0] WR1S;
reg       WR_DELTA;
reg       DCDS, DCD, DDCD, RD_DNCD;
reg [1:0] RD_DNCDS;
reg       DDCD_del;
reg       CTSS, CTS, DCTS, RD_DNCTS;
reg [1:0] RD_DNCTSS;
reg       DCTS_del;
reg       DSRS, DSR, DDSR, RD_DNDSR;
reg [1:0] RD_DNDSRS;
reg       DDSR_del;
reg       RIS, RI, TERI, RD_DNRI;
reg [1:0] RD_DNRIS;
reg       DTERI_del;
reg       NOUT2, NOUT1, NRTS, NDTR, SOUT;
reg       IDCD, ICTS, IRI, IDSR;
reg       LOCAL_RST_SAMP, LOCAL_RST;
reg       BRKTD;

wire CLR_DDCD, WRDDCD, DDCDS, WRDDCD_CLEAR;
wire CLR_DCTS, WRDCTS, WRDCTS_CLEAR, DDCTSS;
wire CLR_DDSR, WRDDSR, WRDDSR_CLEAR, DDDSRS;
wire CLR_DRI, WRDRI, WRDRI_CLEAR, DDRIS;


// Modem Control Register
// Works in CPU timing domain
always @(posedge NWR or posedge MR)
  if (MR)
  begin
    LOOP1 <= 1'b0;
    OUT2 <= 1'b0;
    OUT1 <= 1'b0;
    RTS <= 1'b0;
    DTR  <= 1'b0;
  end
  else if (ADD4)
  begin
    LOOP1 <= DI[4];
    OUT2 <= DI[3];
    OUT1 <= DI[2];
    RTS <= DI[1];
    DTR  <= DI[0];
  end

// Ensure that setting break makes the TX Data output go to 0
always @(TXD or SB)
  BRKTD = ~(TXD & ~SB);

// If loop mode is enabled, all of the modem output lines are
// negated
always @(LOOP1 or OUT2 or OUT1 or RTS or DTR or BRKTD)
begin
  NOUT2 = (~(~LOOP1 & OUT2));
  NOUT1 = (~(~LOOP1 & OUT1));
  NRTS  = (~(~LOOP1 & RTS));
  NDTR  = (~(~LOOP1 & DTR));
  SOUT  = (~(~LOOP1 & BRKTD));
end


// Sample of the modem input lines, with CLK to synchronise

// Read back takes into account loop-backed signals
always @(LOOP1 or OUT2 or DTR or RTS or OUT1 or NDCD or NCTS or NDSR or NRI)
begin
  if (LOOP1)
  begin
    IDCD = OUT2;
    ICTS = RTS;
    IDSR = DTR;
    IRI = OUT1;
  end
  else
  begin
    IDCD = ~NDCD;
    ICTS = ~NCTS;
    IDSR = ~NDSR;
    IRI = ~NRI;
  end
end


// Generation of Modem Status Delta bits

// Possible to generate a delta bit by writing to the appropriate bit
// of the modem status register
always @(posedge NWR or posedge MR)
  if (MR)
    WR1 <= 1'b0;
  else if (ADD6)
    WR1 <= ~WR1S[1];

always @(posedge CLK or posedge MR)
  if (MR)
  begin 
    WR1S[1:0] <= 2'b00;
    WR_DELTA <= 1'b0;
  end
  else
  begin
    WR1S[0] <= WR1;
    WR1S[1] <= WR1S[0];
    WR_DELTA <= (WR1 ^ WR1S[1]); // Synchronise this to CLK domain
  end

// Save contents of Delta bits
always @(posedge NWR or posedge MR)
  if (MR)
  begin
    DDCD_del <= 1'b0;
    DTERI_del <= 1'b0;
    DDSR_del <= 1'b0;
    DCTS_del <= 1'b0;
  end
  else if (ADD6)
  begin
    DDCD_del <= DI[3];
    DTERI_del <= DI[2];
    DDSR_del <= DI[1];
    DCTS_del <= DI[0];
  end

// End of common register and delta code
	
// Start with NDCD
//
// Two stage synchronisation with CLK
// Note Reset has to be active for at least two clocks
// for this circuit to initialise properly
always @(posedge CLK)
begin
  DCDS <= IDCD;
  DCD  <= DCDS;
end

// Sample delta bit
assign DDCDS = ((DCDS ^ DCD) &  LOCAL_RST);

// Generate delta bits

// Generate Local reset for Delta bits
always @(posedge CLK or posedge MR)
begin
   if (MR)
   begin
      LOCAL_RST_SAMP <= 1'b0;
      LOCAL_RST <= 1'b0;
   end
   else
   begin
      LOCAL_RST_SAMP <= 1'b1;
      LOCAL_RST <= LOCAL_RST_SAMP;
   end 
end

always @(posedge CLK or posedge MR)
    if (MR)
	DDCD <= 1'b0;
    else
	DDCD <= (~(CLR_DDCD | WRDDCD_CLEAR) & (DDCD | DDCDS | WRDDCD));

assign WRDDCD = (WR_DELTA & DDCD_del); // Write Either clears or sets
		         	       // only during the delta period
	
assign WRDDCD_CLEAR = (WR_DELTA & ~DDCD_del);

// Clear down with a read of '1' for the delta bit
always @(posedge NRD or posedge MR)
    if (MR)
	RD_DNCD <= 1'b0;
    else if (ADD6 && DA[3])
	RD_DNCD <= ~RD_DNCDS[1];

always @(posedge CLK or posedge MR)
    if (MR)
	RD_DNCDS[1:0] <= 2'b00;
    else
    begin
	RD_DNCDS[0] <= RD_DNCD;
	RD_DNCDS[1] <= RD_DNCDS[0];
    end

assign CLR_DDCD = (RD_DNCD ^ RD_DNCDS[1]);


// Now for CTS
//
// Read back takes into account loop-backed signals

// Two stage synchronisation with CLK
// Note that reset has to be active for at least two
// clocks for this circuit to initialise
always @(posedge CLK)
begin
    CTSS <= ICTS;
    CTS  <= CTSS;
end

// Sample delta bit
assign DDCTSS = ((CTSS ^ CTS) & LOCAL_RST);

// Generate delta bits
always @(posedge CLK or posedge MR)
    if (MR)
	DCTS <= 1'b0;
    else
	DCTS <= (~(CLR_DCTS | WRDCTS_CLEAR) & (DCTS | DDCTSS | WRDCTS));
assign WRDCTS = (WR_DELTA & DCTS_del);
assign WRDCTS_CLEAR = (WR_DELTA & ~DCTS_del);

// Clear down with a read of '1' for the delta bit
always @(posedge NRD or posedge MR)
    if (MR)
	RD_DNCTS <= 1'b0;
    else if (ADD6 && DA[0])
	RD_DNCTS <= ~RD_DNCTSS[1];

always @(posedge CLK or posedge MR)
    if (MR)
	RD_DNCTSS[1:0] <= 2'b00;
    else
    begin
	RD_DNCTSS[0] <= RD_DNCTS;
	RD_DNCTSS[1] <= RD_DNCTSS[0];
    end

assign CLR_DCTS = (RD_DNCTS ^ RD_DNCTSS[1]);


// Now for DSR
//
// Read back takes into account loop-backed signals

// Two stage synchronisation with CLK
// Note that this circuit requires reset to be active
// for at least two clocks to initialise
always @(posedge CLK)
begin
    DSRS <= IDSR;
    DSR  <= DSRS;
end

// Sample delta bit
assign DDDSRS = ((DSRS ^ DSR) & LOCAL_RST);

// Generate delta bits
always @(posedge CLK or posedge MR)
    if (MR)
	DDSR <= 1'b0;
    else
	DDSR <= (~(CLR_DDSR | WRDDSR_CLEAR) & (DDSR | DDDSRS | WRDDSR));

assign WRDDSR = (WR_DELTA & DDSR_del);
assign WRDDSR_CLEAR = (WR_DELTA & ~DDSR_del);
	
// Clear down with a read of '1' for the delta bit
always @(posedge NRD or posedge MR)
    if (MR)
	RD_DNDSR <= 1'b0;
    else if (ADD6 && DA[1])
	RD_DNDSR <= ~RD_DNDSRS[1];

always @(posedge CLK or posedge MR)
    if (MR)
	RD_DNDSRS[1:0] <= 2'b00;
    else
    begin
	RD_DNDSRS[0] <= RD_DNDSR;
	RD_DNDSRS[1] <= RD_DNDSRS[0];
    end

assign CLR_DDSR = (RD_DNDSR ^ RD_DNDSRS[1]);

// Now for RI
// Note that the Delta bit is only generated on the rising
// edge of the RI input
//
// Read back takes into account loop-backed signals

// Two stage synchronisation with CLK
// Note that this circuit requires RESET to be active for
// at least two clocks to initialise
always @(posedge CLK)
begin
    RIS <= IRI;
    RI  <= RIS;
end

// Sample delta bit
assign DDRIS = ((~RIS & RI) & LOCAL_RST);

// Generate delta bits
always @(posedge CLK or posedge MR)
    if (MR)
	TERI <= 1'b0;
    else
	TERI <= (~(CLR_DRI | WRDRI_CLEAR) & (TERI | DDRIS | WRDRI));

assign WRDRI = (WR_DELTA & DTERI_del);
assign WRDRI_CLEAR = (WR_DELTA & ~DTERI_del);
	
// Clear down with a read of '1' for the delta bit
always @(posedge NRD or posedge MR)
    if (MR)
	RD_DNRI <= 1'b0;
    else if (ADD6 && DA[2])
	RD_DNRI <= ~RD_DNRIS[1];

always @(posedge CLK or posedge MR)
    if (MR)
	RD_DNRIS[1:0] <= 2'b00;
    else
    begin
	RD_DNRIS[0] <= RD_DNRI;
	RD_DNRIS[1] <= RD_DNRIS[0];
    end

assign CLR_DRI = (RD_DNRI ^ RD_DNRIS[1]);


endmodule