m3s013an.v

mentor UART IP verilog源码 以通过验证.

// Error FIFO Storage Top Level
// Copyright Mentor Graphics Corporation and Licensors 1999
// V1.000

// This module provides the receive error FIFO top level
// for the M16550a UART.
// This module allows the substitution of a dual port RAM.
// If this is done NVWR needs to be logically ORed with CLK,
// to form the write strobe.

// Revision history:
// V1.000  - 4 March 1999

module m3s013an (
  CLK, IP_D, IP_A, OP_A, NVWR, OP_D
  );

input       CLK;
input [2:0] IP_D;
input [3:0] IP_A, OP_A;
input       NVWR;

output [2:0] OP_D;

wire [2:0] OP_D;
reg [15:0] IpSel, OpSel;
wire [2:0] OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7;
wire [2:0] OP8, OP9, OP10, OP11, OP12, OP13, OP14, OP15;

integer n;

// Input Address decode, generates IP enables
// for each of the FIFO blocks
always @(IP_A)
begin
  for (n=0;n<16;n=n+1)
    if (IP_A == n) IpSel[n] = 1;
    else IpSel[n] = 0;
end

// Output Address decode, generates OP enables
// for each of the FIFO blocks
always @(OP_A)
begin
  for (n=0;n<16;n=n+1)
    if (OP_A == n) OpSel[n] = 1;
    else OpSel[n] = 0;
end

// FIFO Elements instantiated as levels of hierarchy
m3s014an U1(CLK, IP_D, IpSel[0], OpSel[0], NVWR, OP0);
m3s014an U2(CLK, IP_D, IpSel[1], OpSel[1], NVWR, OP1);
m3s014an U3(CLK, IP_D, IpSel[2], OpSel[2], NVWR, OP2);
m3s014an U4(CLK, IP_D, IpSel[3], OpSel[3], NVWR, OP3);
m3s014an U5(CLK, IP_D, IpSel[4], OpSel[4], NVWR, OP4);
m3s014an U6(CLK, IP_D, IpSel[5], OpSel[5], NVWR, OP5);
m3s014an U7(CLK, IP_D, IpSel[6], OpSel[6], NVWR, OP6);
m3s014an U8(CLK, IP_D, IpSel[7], OpSel[7], NVWR, OP7);
m3s014an U9(CLK, IP_D, IpSel[8], OpSel[8], NVWR, OP8);
m3s014an U10(CLK, IP_D, IpSel[9], OpSel[9], NVWR, OP9);
m3s014an U11(CLK, IP_D, IpSel[10], OpSel[10], NVWR, OP10);
m3s014an U12(CLK, IP_D, IpSel[11], OpSel[11], NVWR, OP11);
m3s014an U13(CLK, IP_D, IpSel[12], OpSel[12], NVWR, OP12);
m3s014an U14(CLK, IP_D, IpSel[13], OpSel[13], NVWR, OP13);
m3s014an U15(CLK, IP_D, IpSel[14], OpSel[14], NVWR, OP14);
m3s014an U16(CLK, IP_D, IpSel[15], OpSel[15], NVWR, OP15);


// Output multiplexer
assign
  OP_D = OP0 | OP1 | OP2 | OP3 | OP4 | OP5 | OP6 | OP7 |
         OP8 | OP9 | OP10 | OP11 | OP12 | OP13 | OP14 | OP15;

endmodule