m3s011an.v

mentor UART IP verilog源码 以通过验证.

// Error Bit FIFO Storage
// Copyright Mentor Graphics Corporation and Licensors 1999
// V1.200

// This module provides the error FIFO top level for the M16x50 UART.
// This module forms the 3-bit storage to hold the error flags 
// for each received character of data. 

// Revision history:
// V1.200  - 12 May 1999
//           Modified to use a standard RAM block
// V1.1      Added input RD into this module and Error FIFO elements
//           Updated Error information from Error FIFO elements on posedge of NRD
//           instead of negedge. Introduced signal ERROR_UD to do this.
//	     Removed unused input FIFOE.
//           17/11/97
//
// V1.0    - Created 26/9/96

module m3s011an (
  CLK, MR, RD, NRD, ADD0, ADD5, IP_A, OP_A,
  PTE, FRE, BRI, CharEn, RRST, REmpt, RFull,
  OP_D, FERF
  );

input       CLK, MR, RD, NRD, ADD0, ADD5;
input [3:0] IP_A, OP_A;
input       PTE, FRE, BRI, CharEn, RRST, REmpt, RFull;

output [2:0] OP_D;
output       FERF;

reg [2:0] IpData, OP_D;
reg [3:0] OpAddr;
reg [4:0] CountWr, CountRd;
reg       NVWR, NVRD, FERF;
reg       ErrRead, OpRead1, OpRead2, OpEnab;
wire [2:0] OpData;


// Latch output address
always @(posedge NRD or posedge MR)
  if (MR)
    OpAddr <= 0;
  else
    OpAddr <= OP_A;

// Generate input data from error flags
always @(PTE or FRE or BRI)
  IpData = {PTE,FRE,BRI};

// Generate Read and write enables
always @(CharEn or RFull or REmpt or ADD0 or ADD5)
begin
  NVWR = ~(CharEn & ~RFull);
  NVRD = ~((ADD0 | ADD5) & ~REmpt);
end

// FIFO RAM block
m3s013an U1 (CLK, IpData, IP_A, OpAddr, NVWR, OpData);

// Generate signal indicating the the current output error bits have been read
always @(posedge NRD or posedge MR)
  if (MR)
    ErrRead <= 0;
  else if (ADD5 & ~REmpt)
    ErrRead <= 1;
  else if (ADD0)
    ErrRead <= 0;
always @(posedge RD or posedge MR)
  if (MR)
    OpRead1 <= 0;
  else if (ADD5 | ADD0)
    OpRead1 <= ~(OpRead2 ^ REmpt);
always @(posedge NRD or posedge MR)
  if (MR)
    OpRead2 <= 0;
  else if (ADD0)
    OpRead2 <= OpRead1;

// Enable error output bits when FIFO not empty and
// LSR not read for current output character
always @(OpRead1 or OpRead2 or REmpt)
  OpEnab = ~(OpRead1 ^ OpRead2) & ~REmpt;

always @(OpEnab or OpData)
  OP_D = {3{OpEnab}} & OpData;

// Count errors written to FIFO
always @(posedge CLK or posedge MR)
  if (MR)
    CountWr <= 0;
  else if (RRST | (REmpt & NVWR))
    CountWr <= CountRd;
  else if (~NVWR & (IpData[0] | IpData[1] | IpData[2]))
    CountWr <= CountWr + 1;

// Count errors read from FIFO
always @(posedge NRD or posedge MR)
  if (MR)
    CountRd <= 0;
  else if (~NVRD & ~ErrRead & ~REmpt & (OpData[0] | OpData[1] | OpData[2]))
    CountRd <= CountRd + 1;

// Determine whether there are any valid error in the FIFO
always @(CountWr or CountRd)
  if (CountWr == CountRd)
    FERF = 0;
  else
    FERF = 1;

endmodule