m3s009an.v

mentor UART IP verilog源码 以通过验证.

// Tx Fifo Storage Top Level
// Copyright Mentor Graphics Corporation and Licensors 1999
// V1.0

// This module allows substitution of a dual port RAM.
// If this is done, the external write strobe (NWR) 
// needs to be logically ORed with NVWR. NVRD is the
// read strobe.
//
// Revision history:
// V1.0    - Created 26/9/96


module m3s009an (
  NWR, IP_D, IP_A, OP_A, NVWR, NVRD, OP_D
  );

input [7:0] IP_D;
input [3:0] IP_A, OP_A;
input       NWR, NVWR, NVRD;

output [7:0] OP_D;

wire [7:0] OP_D;
reg [15:0] IpSel, OpSel;
wire [7:0] OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7;
wire [7:0] OP8, OP9, OP10, OP11, OP12, OP13, OP14, OP15;

integer n;

// Input Address decode, generates IP enables
// for each of the FIFO blocks
always @(IP_A)
begin
  for (n=0;n<16;n=n+1)
    if (IP_A == n) IpSel[n] = 1;
    else IpSel[n] = 0;
end

// Output Address decode, generates OP enables
// for each of the FIFO blocks
always @(OP_A)
begin
  for (n=0;n<16;n=n+1)
    if (OP_A == n) OpSel[n] = 1;
    else OpSel[n] = 0;
end

// FIFO Elements instantiated as levels of hierarchy
m3s012an U1(NWR, IP_D, IpSel[0], OpSel[0], NVWR, NVRD, OP0);
m3s012an U2(NWR, IP_D, IpSel[1], OpSel[1], NVWR, NVRD, OP1);
m3s012an U3(NWR, IP_D, IpSel[2], OpSel[2], NVWR, NVRD, OP2);
m3s012an U4(NWR, IP_D, IpSel[3], OpSel[3], NVWR, NVRD, OP3);
m3s012an U5(NWR, IP_D, IpSel[4], OpSel[4], NVWR, NVRD, OP4);
m3s012an U6(NWR, IP_D, IpSel[5], OpSel[5], NVWR, NVRD, OP5);
m3s012an U7(NWR, IP_D, IpSel[6], OpSel[6], NVWR, NVRD, OP6);
m3s012an U8(NWR, IP_D, IpSel[7], OpSel[7], NVWR, NVRD, OP7);
m3s012an U9(NWR, IP_D, IpSel[8], OpSel[8], NVWR, NVRD, OP8);
m3s012an U10(NWR, IP_D, IpSel[9], OpSel[9], NVWR, NVRD, OP9);
m3s012an U11(NWR, IP_D, IpSel[10], OpSel[10], NVWR, NVRD, OP10);
m3s012an U12(NWR, IP_D, IpSel[11], OpSel[11], NVWR, NVRD, OP11);
m3s012an U13(NWR, IP_D, IpSel[12], OpSel[12], NVWR, NVRD, OP12);
m3s012an U14(NWR, IP_D, IpSel[13], OpSel[13], NVWR, NVRD, OP13);
m3s012an U15(NWR, IP_D, IpSel[14], OpSel[14], NVWR, NVRD, OP14);
m3s012an U16(NWR, IP_D, IpSel[15], OpSel[15], NVWR, NVRD, OP15);

// Output multiplexer
assign
  OP_D = OP0 | OP1 | OP2 | OP3 | OP4 | OP5 | OP6 | OP7 |
         OP8 | OP9 | OP10 | OP11 | OP12 | OP13 | OP14 | OP15;

endmodule