m3s014an.v

mentor UART IP verilog源码 以通过验证.

// Error FIFO Element Cell
// Copyright Mentor Graphics Corporation and Licensors 1999
// V1.100

// This module provides the error FIFO elements for the M16550a UART.

// Revision history:
// V1.100  - 15 June 1999
//           Changed constant from 2'b0 to 2'b00 to clear lint warning (ECN 1242)
// V1.000  - 4 March 1999


module m3s014an (
  CLK, IP_D, IpSel, OpSel, NVWR, OP_D
  );

input       CLK;
input [2:0] IP_D;
input       IpSel, OpSel, NVWR;

output [2:0] OP_D;

reg [2:0] Data, OP_D;

always @(posedge CLK)
  if (IpSel & ~NVWR)
    Data <= IP_D;

always @(OpSel or Data)
  if (OpSel)
    OP_D = Data;
  else
    OP_D = 2'b00;

endmodule