m3s007an.v

mentor UART IP verilog源码 以通过验证.

// Transmit FIFO Controller
// Copyright Mentor Graphics Corporation and Licensors 1999
// V1.500

// This module provides the transmit FIFO control
// for the M16550a UART.

// Revision history:
// V1.500 - 29 September 1999
//          Remove signal THold1 from this module as superflous (ECN 1267)
// V1.400 - 12 May 1999
//          Signals renamed
// V1.3   - Added DELTA_TRST output 10/11/97
// V1.2   - TFULL modified to match the real part more closely
// V1.1   - OP_A and IP_A reduced to 4-bits in the port list
// V1.0   - Created 26/9/96


module m3s007an (
  CLK, MR, NWR, ADD0, ADD2, LoadTxBuff,
  DI2, DI0, FIFOE,
  TOP_A, TIP_A, TEmpt, TFull, NVWR, NVRD, DELTA_TRST
  );

input CLK, MR, NWR, ADD0, ADD2, LoadTxBuff;
input DI2, DI0, FIFOE;

output [3:0] TOP_A, TIP_A;
output       TEmpt, TFull;
output       NVWR, NVRD;
output       DELTA_TRST;  // Delta version of TX FIFO reset

reg [3:0] TOP_A, TIP_A;
reg [4:0] OP_A, IP_A, TOffset;
reg [1:0] TSR;
reg       DTRST, TRST, TEmpt, TFull;
reg       NVRD, NVWR, DELTA_TRST;


// Generate reset for Tx FIFO counter using bit 2 in FCR
always @(posedge NWR or posedge MR)
  if (MR)
    DTRST <= 0;
  else if (ADD2 & DI2 & DI0)	// Ensures fifo are enabled (DI0)
    DTRST <= ~TSR[1];

always @(posedge CLK or posedge MR)
  if (MR)
    TSR <= 2'b00;
  else
    TSR <= {TSR[0],DTRST};

// Holds FIFOs in reset when disabled
always @(DTRST or TSR or FIFOE)
begin
  TRST = ((DTRST ^ TSR[1]) | ~FIFOE);
  DELTA_TRST = (DTRST ^ TSR[1]);
end

// Prevent writing if FIFO is full
always @(ADD0 or TOffset or FIFOE)
  NVWR = ~(ADD0 & ~TOffset[4] & FIFOE);

// Prevent reading if FIFO is empty
always @(TEmpt or LoadTxBuff)
  NVRD = (TEmpt | ~LoadTxBuff);

// Counter is held in reset when FIFOs are disabled
//
// Tx FIFO input counter
always @(posedge NWR or posedge MR)
  if (MR)
    IP_A <= 0;
  else if (~NVWR)      // Only write to FIFO when not full
    IP_A <= IP_A + 1;

// Tx FIFO output counter
always @(posedge CLK or posedge MR)
  if (MR)
    OP_A <= 0;
  else if (TRST)
    OP_A <= IP_A;        // Synchronous reset
  else if (~NVRD)        // Only read from FIFO when it contains something
    OP_A <= OP_A + 1;

// Works out difference between input and output pointers.
always @(IP_A or OP_A)
  TOffset = (IP_A - OP_A);

// Decide if FIFO is below trigger level or holding 1 character
always @(TOffset)
begin
  TEmpt = (TOffset == 0);
end

// IP_A & OP_A reduced by 1 bit for exporting to upper level
always @(IP_A or OP_A)
begin
  TIP_A = IP_A[3:0];
  TOP_A = OP_A[3:0];
end

always @(posedge CLK or posedge MR)
  if (MR)
    TFull <= 0;
  else
    TFull <= ((TFull | TOffset[4]) & ~TEmpt);

endmodule